Contains the source code from the course work throughout my undergraduate Computer Engineering degree at Brigham Young University. There is a mixture of Go, Python, C, C++, Java, VHDL, Verilog, Matlab, Bash, Assembly, etc..
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platform.c 2.0KB

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  1. /*
  2. * Copyright (c) 2010-2011 Xilinx, Inc. All rights reserved.
  3. *
  4. * Xilinx, Inc.
  5. * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
  6. * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
  7. * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
  8. * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
  9. * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
  10. * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
  11. * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
  12. * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
  13. * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
  14. * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
  15. * AND FITNESS FOR A PARTICULAR PURPOSE.
  16. *
  17. */
  18. #include "xparameters.h"
  19. #include "xil_cache.h"
  20. #include "platform_config.h"
  21. #ifdef STDOUT_IS_PS7_UART
  22. #include "xuartps.h"
  23. #elif defined(STDOUT_IS_16550)
  24. #include "xuartns550_l.h"
  25. #endif
  26. #define UART_BAUD 9600
  27. void
  28. enable_caches()
  29. {
  30. #ifdef __PPC__
  31. Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
  32. Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
  33. #elif __MICROBLAZE__
  34. #ifdef XPAR_MICROBLAZE_USE_ICACHE
  35. Xil_ICacheEnable();
  36. #endif
  37. #ifdef XPAR_MICROBLAZE_USE_DCACHE
  38. Xil_DCacheEnable();
  39. #endif
  40. #endif
  41. }
  42. void
  43. disable_caches()
  44. {
  45. Xil_DCacheDisable();
  46. Xil_ICacheDisable();
  47. }
  48. void
  49. init_uart()
  50. {
  51. #ifdef STDOUT_IS_PS7_UART
  52. /* Use the PS UART for Zynq devices */
  53. XUartPs Uart_Ps_0;
  54. XUartPs_Config *Config_0 = XUartPs_LookupConfig(UART_DEVICE_ID);
  55. XUartPs_CfgInitialize(&Uart_Ps_0, Config_0, Config_0->BaseAddress);
  56. XUartPs_SetBaudRate(&Uart_Ps_0, UART_BAUD);
  57. #elif defined(STDOUT_IS_16550)
  58. XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
  59. XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
  60. #endif
  61. }
  62. void
  63. init_platform()
  64. {
  65. enable_caches();
  66. init_uart();
  67. }
  68. void
  69. cleanup_platform()
  70. {
  71. disable_caches();
  72. }