82 lines
2.0 KiB
C
82 lines
2.0 KiB
C
/*
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* Copyright (c) 2010-2011 Xilinx, Inc. All rights reserved.
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*
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* Xilinx, Inc.
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
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* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
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* STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
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* IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
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* FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
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* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
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* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
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* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
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* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE.
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*
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*/
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#include "xparameters.h"
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#include "xil_cache.h"
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#include "platform_config.h"
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#ifdef STDOUT_IS_PS7_UART
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#include "xuartps.h"
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#elif defined(STDOUT_IS_16550)
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#include "xuartns550_l.h"
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#endif
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#define UART_BAUD 9600
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void
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enable_caches()
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{
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#ifdef __PPC__
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Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK);
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Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK);
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#elif __MICROBLAZE__
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#ifdef XPAR_MICROBLAZE_USE_ICACHE
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Xil_ICacheEnable();
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#endif
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#ifdef XPAR_MICROBLAZE_USE_DCACHE
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Xil_DCacheEnable();
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#endif
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#endif
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}
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void
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disable_caches()
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{
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Xil_DCacheDisable();
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Xil_ICacheDisable();
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}
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void
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init_uart()
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{
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#ifdef STDOUT_IS_PS7_UART
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/* Use the PS UART for Zynq devices */
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XUartPs Uart_Ps_0;
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XUartPs_Config *Config_0 = XUartPs_LookupConfig(UART_DEVICE_ID);
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XUartPs_CfgInitialize(&Uart_Ps_0, Config_0, Config_0->BaseAddress);
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XUartPs_SetBaudRate(&Uart_Ps_0, UART_BAUD);
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#elif defined(STDOUT_IS_16550)
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XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD);
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XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS);
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#endif
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}
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void
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init_platform()
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{
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enable_caches();
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init_uart();
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}
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void
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cleanup_platform()
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{
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disable_caches();
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}
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