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adding ecen 320 final project

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This commit is contained in:
Derek McQuay 2016-04-10 09:22:51 -07:00
parent 9d4aab12b8
commit 4014513685
24 changed files with 7760 additions and 0 deletions
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ecen320/README.txt Normal file
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AUTHORS:
Aaron Norris
Derek McQuay
COURSE:
ECEN 320
Winter 2014
Dr. Mike Wirthlin
Brigham Young University
SUMMARY:
This is a color based encryption/decryption program that sends its data
over UART
INSTRUCTIONS:
Hardware:
Nexys 2 FPGA (2)
Serial Cable (1)
Serial Null Modem (1)
Computer (1)
ps2 Keyboard (1)
Vga monitor & cable (2)
Running:
Load rx onto one board, and plug in the ps2 keyboard.
Load tx onto the other board.
Connect the two boards with the null modem and the serial cable.
You can now send messages between the boards.
As long as background color is the same on the two screens, the
message will appear on both.
When the colors mismatch, gibberish will print.
Move the switches to select colors.
FUTURE WORK:
Remove the jitter on the tx. After hours of work, we can't get the
display quite right.
Load an image into the memory, and read it pixel by pixel using one
pixel for one character. This way both sides need an identical
picture to send and recieve. Use switch 8 to indicate this option.
Write it so each board does both rx and tx. Select by button?
PROJECT BUILD OPTIONS:
Normal synthsis
PROJECT SIZE:
RX:
188 Slices used (2%)
approx 3366 lines of code (some identical to tx)
TX:
373 Slices used (8%)
approx 4006 lines of code (some identical to rx)
This is larger because of the ps2 code for the keyboard.

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ecen320/Spartan3EMaster.ucf Normal file
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# This file is a general .ucf for Nexys2 rev A board
# To use it in a project:
# - remove or comment the lines corresponding to unused pins
# - rename the used signals according to the project
## clock pin for Nexys 2 Board
NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
##NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
#
## Leds
NET "Led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
NET "Led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
NET "Led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
NET "Led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
#NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4
#NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5
#NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6
#NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7
## Switches
#NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
#NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
#NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
#NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
#NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
#NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
#NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
#NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
## Buttons
#NET "btn<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
#NET "btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
#NET "btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
#NET "btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
## 7 segment display
#NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
#NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
#NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
#NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
#NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
#NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
#NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
#NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
#NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
#NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
#NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
#NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
## VGA Connector
#NET "vgaRed<1>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
#NET "vgaRed<2>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
#NET "vgaRed<3>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
#NET "vgaGreen<1>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
#NET "vgaGreen<2>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
#NET "vgaGreen<3>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
#NET "vgaBlue<2>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
#NET "vgaBlue<3>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
#NET "Hsync" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
#NET "Vsync" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
## RS232 connector
#NET "RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
#NET "RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
## PS/2 connector
#NET "PS2C" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
#NET "PS2D" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
## onBoard Cellular RAM and StrataFlash
#NET "MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
#NET "MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
#NET "RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
#NET "RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
#NET "RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
#NET "RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
#NET "RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
#NET "RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
#NET "FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
#NET "MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
#NET "MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
#NET "MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
#NET "MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
#NET "MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
#NET "MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
#NET "MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
#NET "MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
#NET "MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
#NET "MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
#NET "MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
#NET "MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
#NET "MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
#NET "MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
#NET "MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
#NET "MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
#NET "MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
#NET "MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
#NET "MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
#NET "MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
#NET "MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
#NET "MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
#NET "MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
#NET "MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
#NET "MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
#NET "MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
#NET "MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
#NET "MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
#NET "MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
#NET "MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
#NET "MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
#NET "MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
#NET "MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
#NET "MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
#NET "MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
#NET "MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
#NET "MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
#NET "MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
#NET "MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
## FX2 connector
#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
## 12 pin connectors
#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
## onBoard USB controller
#NET "EppAstb" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
#NET "EppDstb" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
#NET "UsbFlag" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
#NET "EppWait" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
#NET "EppDB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
#NET "EppDB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
#NET "EppDB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
#NET "EppDB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
#NET "EppDB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
#NET "EppDB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
#NET "EppDB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
#NET "EppDB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
#NET "UsbClk" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
#NET "UsbOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
#NET "UsbWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SWLR
#NET "UsbPktEnd" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
#NET "UsbDir" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
#NET "UsbAdr<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
#NET "UsbAdr<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
##NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY

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# This file is a general .ucf for Nexys2 rev A board
# To use it in a project:
# - remove or comment the lines corresponding to unused pins
# - rename the used signals according to the project
## clock pin for Nexys 2 Board
NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
#NET "clk" TNM_NET = "clk";
#TIMESPEC "TS_clk" = PERIOD "clk" 20 ns HIGH 50 %;
##NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
#
## Leds
#NET "Led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
#NET "Led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
#NET "Led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
#NET "Led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
#NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4
#NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5
#NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6
#NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7
## Switches
NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
## Buttons
NET "btn<0>" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
NET "btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
NET "btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
NET "btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
## 7 segment display
NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
## VGA Connector
NET "rgb<7>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
NET "rgb<6>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
NET "rgb<5>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
NET "rgb<4>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
NET "rgb<3>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
NET "rgb<2>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
NET "rgb<1>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
NET "rgb<0>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
NET "hs_out" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
NET "vs_out" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
## RS232 connector
NET "rx_in" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
#NET "RsTx" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
## PS/2 connector
#NET "PS2C" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
#NET "PS2D" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
## onBoard Cellular RAM and StrataFlash
#NET "MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
#NET "MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
#NET "RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
#NET "RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
#NET "RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
#NET "RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
#NET "RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
#NET "RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
#NET "FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
#NET "MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
#NET "MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
#NET "MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
#NET "MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
#NET "MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
#NET "MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
#NET "MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
#NET "MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
#NET "MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
#NET "MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
#NET "MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
#NET "MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
#NET "MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
#NET "MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
#NET "MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
#NET "MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
#NET "MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
#NET "MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
#NET "MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
#NET "MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
#NET "MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
#NET "MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
#NET "MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
#NET "MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
#NET "MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
#NET "MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
#NET "MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
#NET "MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
#NET "MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
#NET "MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
#NET "MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
#NET "MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
#NET "MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
#NET "MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
#NET "MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
#NET "MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
#NET "MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
#NET "MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
#NET "MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
## FX2 connector
#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
## 12 pin connectors
#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
## onBoard USB controller
#NET "EppAstb" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
#NET "EppDstb" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
#NET "UsbFlag" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
#NET "EppWait" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
#NET "EppDB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
#NET "EppDB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
#NET "EppDB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
#NET "EppDB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
#NET "EppDB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
#NET "EppDB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
#NET "EppDB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
#NET "EppDB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
#NET "UsbClk" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
#NET "UsbOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
#NET "UsbWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SWLR
#NET "UsbPktEnd" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
#NET "UsbDir" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
#NET "UsbAdr<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
#NET "UsbAdr<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
##NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY

76
ecen320/rx_decoder/charGen.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity charGen is
port(
clk: in std_logic;
char_we: in std_logic;
char_value: in std_logic_vector(7 downto 0);
char_addr: in std_logic_vector(11 downto 0);
pixel_x, pixel_y: in std_logic_vector(9 downto 0);
pixel_out: out std_logic
);
end charGen;
architecture charGen_arch of charGen is
component char_mem
port(
clk: in std_logic;
char_read_addr : in std_logic_vector(11 downto 0);
char_write_addr: in std_logic_vector(11 downto 0);
char_we : in std_logic;
char_write_value : in std_logic_vector(7 downto 0);
char_read_value : out std_logic_vector(7 downto 0)
);
end component;
component font_rom
port(
clk: in std_logic;
addr: in std_logic_vector(10 downto 0);
data: out std_logic_vector(7 downto 0)
);
end component;
signal rom_addr: std_logic_vector(10 downto 0);
signal ram_read_addr: std_logic_vector(11 downto 0);
signal ram_value: std_logic_vector(7 downto 0);
signal myselect: std_logic_vector(2 downto 0);
signal temp1: std_logic_vector(2 downto 0);
signal rom_dataout: std_logic_vector(7 downto 0);
begin
myram: char_mem
port map(clk=>clk, char_read_addr=>ram_read_addr, char_write_addr=>char_addr, char_we=>char_we, char_write_value=>char_value, char_read_value=>ram_value
);
myrom: font_rom
port map(clk=>clk, addr=>rom_addr, data=>rom_dataout
);
process(clk)
begin
if(rising_edge(clk)) then
temp1 <= pixel_x(2 downto 0);
myselect <= temp1;
end if;
end process;
with myselect select
pixel_out <= rom_dataout(7) when "000",
rom_dataout(6) when "001",
rom_dataout(5) when "010",
rom_dataout(4) when "011",
rom_dataout(3) when "100",
rom_dataout(2) when "101",
rom_dataout(1) when "110",
rom_dataout(0) when others;
ram_read_addr <= pixel_y(8 downto 4) & pixel_x(9 downto 3);
rom_addr <= ram_value(6 downto 0) & pixel_y(3 downto 0);
end charGen_arch;

241
ecen320/rx_decoder/charGen_top.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity charGen_top is
port(
clk: in std_logic;
rgb: out std_logic_vector(7 downto 0);
hs_out, vs_out: out std_logic;
sw: in std_logic_vector(7 downto 0);
seg : out std_logic_vector(6 downto 0);
an : out std_logic_vector(3 downto 0) := "1100";
dp : out std_logic;
rx_in : in std_logic;
btn: in std_logic_vector(3 downto 0)
);
end charGen_top;
architecture top_charGen of charGen_top is
component charGen
port(
clk: in std_logic;
char_we: in std_logic;
char_value: in std_logic_vector(7 downto 0);
char_addr: in std_logic_vector(11 downto 0);
pixel_x, pixel_y: in std_logic_vector(9 downto 0);
pixel_out: out std_logic
);
end component;
component vga_timing is
port(
clk, rst: in std_logic;
HS, VS: out std_logic;
pixel_x, pixel_y: out std_logic_vector(9 downto 0);
last_column, last_row: out std_logic;
blank: out std_logic
);
end component;
component seven_segment_display
generic(
COUNTER_BITS: natural := 15
);
port(
clk: in std_logic;
data_in: in std_logic_vector(15 downto 0);
dp_in: in std_logic_Vector(3 downto 0);
blank: in std_logic_vector(3 downto 0);
seg : out std_logic_vector(6 downto 0);
dp : out std_logic;
an : out std_logic_vector(3 downto 0)
);
end component;
component rx
port(
clk: in std_logic;
rst: in std_logic;
data_out: out std_logic_vector(7 downto 0);
data_strobe: out std_logic;
rx_in: in std_logic;
rx_busy:out std_logic
);
end component;
signal temp_x,temp_y: std_logic_vector(9 downto 0);
signal hs,vs: std_logic;
signal temp_hs,temp_vs: std_logic := '0';
signal reset: std_logic := '0';
signal dp_in: std_logic_vector(3 downto 0) := "0000";
signal blank4: std_logic_vector(3 downto 0) := (others=>'0');
signal data_in: std_logic_vector(15 downto 0) := (others=>'0');
signal pixel_out: std_logic;
signal count: natural := 0;
signal count_next: natural;
signal count_en: std_logic;
signal char_we: std_logic;
signal row_position, column_position: natural := 0;
signal row_next, column_next: natural;
signal row_en: std_logic;
signal char_write_addr: std_logic_vector(11 downto 0) := (others=>'0');
signal blank: std_logic := '0';
signal font_color: std_logic_vector(7 downto 0) := (others=>'0');
signal back_color: std_logic_vector(7 downto 0) := (others=>'0');
-------rx top signals
signal reset1: std_logic := '0';
signal data_out2: std_logic_vector(7 downto 0) := (others=>'0');
signal data_strobe: std_logic;
signal reg_left,reg_right: std_logic_vector(7 downto 0) := (others=>'0');
signal reg_right_temp: std_logic_vector(7 downto 0);
signal delay_data1, delay_data2: std_logic;
signal temp: std_logic_vector(15 downto 0) := (others=>'0');
signal decrypt: std_logic_vector(15 downto 0) := (others=>'0');
signal go: std_logic := '0';
begin
bottom_level: vga_timing
port map(clk=>clk, rst=>reset, pixel_x=>temp_x, pixel_y=>temp_y, blank=>blank,
HS=>hs, VS=>vs, last_column=>open, last_row=>open
);
bottom_charGen: charGen
port map(clk=>clk, char_we=>char_we, char_value=>reg_right, char_addr=>char_write_addr, pixel_x=>temp_x, pixel_y=>temp_y, pixel_out=>pixel_out
);
-- bottom_segment: seven_segment_display
-- generic map(COUNTER_BITS=>15)
-- port map(clk=>clk, an=>an, seg=>seg, dp=>dp, blank=>blank4,
-- data_in=>data_in, dp_in=>dp_in
-- );
--- this is from rx_Top-----
bottom_segment: seven_segment_display
generic map(COUNTER_BITS=>15)
port map(clk=>clk, an=>an, seg=>seg, dp=>dp, blank=>blank4,
data_in=>temp, dp_in=>dp_in
);
bottom_rx: rx
port map(clk=>clk, rst=>reset1, data_out=>data_out2,
data_strobe=>data_strobe, rx_in=>delay_data2, rx_busy=>open
);
------------rx top code-------------------------
--temp <= (reg_left & reg_right);
process(clk)
begin
if(rising_edge(clk)) then
delay_data1 <= rx_in;
delay_data2 <= delay_data1;
if(data_strobe='1') then
reg_left <= reg_right;
reg_right <= std_logic_vector(unsigned(data_out2) - unsigned(sw));
end if;
end if;
end process;
------------end of rx top code-----------------
---------------***********************************-----------------------------
-- to do decryption you need to make temp signal and take reg_right
-- and do the subtraction and pipe that temp signal into char_gen line 104
---------------***********************************-----------------------------
--reg_right_temp <= reg_right;
decrypt <= std_logic_vector(std_logic_vector(unsigned(reg_left) - unsigned(sw)) & std_logic_vector(unsigned(reg_right) - unsigned(sw)));
temp <= decrypt;
--data_in <= "00000000" & temp;
data_in <= temp;
-- delaying counter
process(clk)
begin
if(rising_edge(clk)) then
count <= count_next;
end if;
end process;
count_next <= 0 when count=4000000 else
count + 1;
count_en <= '1' when count=4000000 else
'0';
-- row_position, column_position logic
row_next <= row_position+1 when row_position < 30 else
0;
column_next <= column_position+1 when column_position < 79 else
0;
row_en <= '1' when column_position = 79 else
'0';
char_write_addr <= std_logic_vector(to_unsigned(row_position,5)) & std_logic_vector(to_unsigned(column_position,7));
font_color <= sw(7 downto 0);
back_color <= not sw(7 downto 0);
-- color logic
rgb <= std_logic_vector(font_color) when pixel_out='1' else
std_logic_vector(back_color) when blank = '0' else
"00000000";
char_we <= '1' when count_en='1' and go = '1' else
'0';
process(clk)
begin
if(rising_edge(clk)) then
if(data_strobe = '1') then
go <='1';
end if;
if(char_we = '1') then
go <='0';
end if;
end if;
end process;
-- button logic
process(clk,btn,count_en,go)
begin
if(rising_edge(clk)) then
if (btn(3)='1') then
reset <= '1';
column_position <= 0;
row_position <= 0;
elsif (go = '1') then
if(count_en='1') then
reset <= '0';
column_position <= column_next;
if(row_en='1') then
row_position <= row_next;
-- font_color <= font_color+1;
if(row_position=0) then
--back_color <= back_color+1;
end if;
end if;
end if;
else
reset <= '0';
end if;
end if;
end process;
-- making delays for HS, VS
process(clk,hs,vs)
begin
if(rising_edge(clk)) then
temp_hs <= hs;
temp_vs <= vs;
hs_out <= temp_hs;
vs_out <= temp_vs;
end if;
end process;
end top_charGen;

341
ecen320/rx_decoder/char_mem.vhd Normal file
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-- VGA Character Memory
--
-- This memory can store 128x32 characters where each character is
-- 8 bits. The memory is dual ported providing a port
-- to read the characters and a port to write the characters.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity char_mem is
port(
clk: in std_logic;
char_read_addr : in std_logic_vector(11 downto 0);
char_write_addr: in std_logic_vector(11 downto 0);
char_we : in std_logic;
char_write_value : in std_logic_vector(7 downto 0);
char_read_value : out std_logic_vector(7 downto 0)
);
end char_mem;
architecture arch of char_mem is
constant CHAR_RAM_ADDR_WIDTH: integer := 12; -- 2^7 X 2^5
constant CHAR_RAM_WIDTH: integer := 8; -- 8 bits per character
type char_ram_type is array (0 to 2**CHAR_RAM_ADDR_WIDTH-1)
of std_logic_vector(CHAR_RAM_WIDTH-1 downto 0);
signal read_a : std_logic_vector(11 downto 0);
-- character memory signal
signal char_ram : char_ram_type := (
-- Initial Value of character memory
-- Line 0
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 1
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 2
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 3
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 4
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 5
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
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X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 21
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 22
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 23
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 24
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 25
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 26
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 27
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 28
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 29
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"52",--End of visible characters
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 30
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X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"52",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"52",
-- Line 31
X"60",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"52",X"52"
);
begin
-- character memory concurrent statement
process(clk)
begin
if (clk'event and clk='1') then
if (char_we = '1') then
char_ram(to_integer(unsigned(char_write_addr))) <= char_write_value;
end if;
read_a <= char_read_addr;
end if;
end process;
char_read_value <= char_ram(to_integer(unsigned(read_a)));
end arch;

2215
ecen320/rx_decoder/font_rom.vhd Normal file
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179
ecen320/rx_decoder/rx.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rx is
generic(
CLK_RATE: natural := 50_000_000;
BAUD_RATE: natural := 19_200
);
port(
clk: in std_logic;
rst: in std_logic;
rx_in: in std_logic;
data_out: out std_logic_vector(7 downto 0);
data_strobe: out std_logic;
rx_busy:out std_logic
--send_character: in std_logic;
);
end rx;
architecture receive_arch of rx is
function log2c(n: integer) return integer is
variable m, p: integer;
begin
m := 0;
p := 1;
while p<n loop
m:= m+1;
p:=p*2;
end loop;
return m;
end log2c;
constant BIT_COUNTER_MAX_VAL : Natural := CLK_RATE / BAUD_RATE - 1;
constant BIT_COUNTER_BITS : Natural := log2c(BIT_COUNTER_MAX_VAL);
signal counter: unsigned(BIT_COUNTER_BITS downto 0) := (others=>'0');
signal counter_next: unsigned(BIT_COUNTER_BITS downto 0);
type fsm_state_type is
(power_up,idle,strt,b0,b1,b2,b3,b4,b5,b6,b7,stp);
signal state_reg, state_next: fsm_state_type;
-- BitTimer signal
signal rx_bit: std_logic := '0' ;
signal rx_bit_half: std_logic := '0' ;
begin
-- FSM
process(clk,rst)
begin
if(rst='1') then
state_reg <= idle;
elsif(clk'event and clk='1') then
state_reg <= state_next;
end if;
end process;
process(state_reg,rx_in,rx_bit,rx_bit_half)
begin
state_next <= state_reg;
rx_busy <= '1';
data_strobe <= '0';
case state_reg is
when idle =>
rx_busy <= '0';
if(rx_in='0') then
state_next <= strt;
end if;
when strt =>
if(rx_bit='1') then
state_next <= b0;
end if;
when b0 =>
if(rx_bit='1') then
state_next <= b1;
else
if(rx_bit_half='1') then
data_out(0) <= rx_in;
end if;
end if;
when b1 =>
if(rx_bit='1') then
state_next <= b2;
else
if(rx_bit_half='1') then
data_out(1) <= rx_in;
end if;
end if;
when b2 =>
if(rx_bit='1') then
state_next <= b3;
else
if(rx_bit_half='1') then
data_out(2) <= rx_in;
end if;
end if;
when b3 =>
if(rx_bit='1') then
state_next <= b4;
else
if(rx_bit_half='1') then
data_out(3) <= rx_in;
end if;
end if;
when b4 =>
if(rx_bit='1') then
state_next <= b5;
else
if(rx_bit_half='1') then
data_out(4) <= rx_in;
end if;
end if;
when b5 =>
if(rx_bit='1') then
state_next <= b6;
else
if(rx_bit_half='1') then
data_out(5) <= rx_in;
end if;
end if;
when b6 =>
if(rx_bit='1') then
state_next <= b7;
else
if(rx_bit_half='1') then
data_out(6) <= rx_in;
end if;
end if;
when b7 =>
if(rx_bit='1') then
state_next <= stp;
else
if(rx_bit_half='1') then
data_out(7) <= rx_in;
end if;
end if;
when stp =>
if(rx_bit='0') then
state_next <= stp;
elsif(rx_bit='1' and rx_in='1') then
state_next <= idle;
data_strobe <= '1';
elsif (rx_bit='1' and rx_in='0') then
state_next <= power_up;
end if;
when power_up =>
if(rx_in='1') then
state_next <= idle;
end if;
end case;
end process;
--data_strobe <= '1' when (state_reg=stp) and (state_next=idle) else
-- '0';
-- BitTimer
process(clk,rst)
begin
if(rst='1') then
counter <= (others=>'0');
elsif(clk'event and clk='1') then
counter <= counter_next;
end if;
end process;
counter_next <= (others=>'0') when counter = to_unsigned(BIT_COUNTER_MAX_VAL,BIT_COUNTER_BITS) else
(others=>'0') when state_reg = idle else
counter+1;
rx_bit <= '1' when counter = to_unsigned(BIT_COUNTER_MAX_VAL,BIT_COUNTER_BITS) else
'0';
rx_bit_half <= '1' when counter= to_unsigned(BIT_COUNTER_MAX_VAL, BIT_COUNTER_BITS)/2 else
'0';
end receive_arch;

78
ecen320/rx_decoder/seven_segment_display.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity seven_segment_display is
generic(
COUNTER_BITS: natural := 15
);
port(
clk: in std_logic;
data_in: in std_logic_vector(15 downto 0);
dp_in: in std_logic_vector(3 downto 0);
blank: in std_logic_vector(3 downto 0);
seg: out std_logic_vector(6 downto 0);
dp: out std_logic;
an: out std_logic_vector(3 downto 0)
);
end seven_segment_display;
architecture seven_arch of seven_segment_display is
--signal which_sym: std_logic_vector(3 downto 0);
signal mydatain, an_temp: std_logic_vector(3 downto 0);
signal r_reg: unsigned(COUNTER_BITS-1 downto 0):=(others=>'0');
signal r_next: unsigned(COUNTER_BITS-1 downto 0);
signal anode_select: std_logic_vector(1 downto 0);
begin
--register
process(clk)
begin
if clk'event and clk='1' then
r_reg <= r_next;
end if;
end process;
--next-state logic
process(r_reg)
begin
r_next <= r_reg+1;
end process;
anode_select <= std_logic_vector(r_reg(COUNTER_BITS-1 downto COUNTER_BITS-2));
with mydatain select
seg <= "1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;
mydatain <= data_in(3 downto 0) when anode_select = "00" else
data_in(7 downto 4) when anode_select = "01" else
data_in(11 downto 8) when anode_select = "10" else
data_in(15 downto 12);
dp <= not dp_in(0) when anode_select="00" else
not dp_in(1) when anode_select="01" else
not dp_in(2) when anode_select="10" else
not dp_in(3);
an_temp <= "1110" when anode_select="00" else
"1101" when anode_select="01" else
"1011" when anode_select="10" else
"0111" when anode_select="11" else
"0000";
an <= an_temp or blank;
end seven_arch;

78
ecen320/rx_decoder/vga_timing.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_timing is
port(
clk, rst: in std_logic;
HS, VS: out std_logic;
pixel_x, pixel_y: out std_logic_vector(9 downto 0);
last_column, last_row: out std_logic;
blank: out std_logic
);
end vga_timing;
architecture vga_arch of vga_timing is
signal pixel_en: std_logic := '0';
signal column: unsigned(9 downto 0) := (others=>'0');
signal column_next: unsigned(9 downto 0);
signal row_en: std_logic;
signal row: unsigned(9 downto 0) := (others=>'0');
signal row_next: unsigned(9 downto 0);
begin
-- pixel clock
process(clk,rst)
begin
if(rst='1') then
pixel_en <= '0';
elsif(clk'event and clk='1') then
pixel_en <= not pixel_en;
end if;
end process;
-- horizontal counter
process(pixel_en,rst)
begin
if(rst='1') then
column <= (others=>'0');
elsif(pixel_en'event and pixel_en='1') then
column <= column_next;
end if;
end process;
column_next <= (others=>'0') when column=799 else
column + 1;
row_en <= '1' when column=799 else
'0';
-- vertical counter
process(row_en,rst)
begin
if(rst='1') then
row <= (others=>'0');
elsif(row_en'event and row_en='1') then
row <= row_next;
end if;
end process;
row_next <= (others=>'0') when row=520 else
row + 1;
--output logic
pixel_x <= std_logic_vector(column);
pixel_y <= std_logic_vector(row);
last_column <= '1' when column=639 else
'0';
last_row <= '1' when row=479 else
'0';
HS <= '0' when column >= 656 and column <= 751 else
'1';
VS <= '0' when row >= 490 and row <= 491 else
'1';
blank <= '0' when column >= 0 and column <= 639 and row >= 0 and row <= 479 else
'1';
end vga_arch;

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# This file is a general .ucf for Nexys2 rev A board
# To use it in a project:
# - remove or comment the lines corresponding to unused pins
# - rename the used signals according to the project
## clock pin for Nexys 2 Board
NET "clk" LOC = "B8"; # Bank = 0, Pin name = IP_L13P_0/GCLK8, Type = GCLK, Sch name = GCLK0
##NET "clk1" LOC = "U9"; # Bank = 2, Pin name = IO_L13P_2/D4/GCLK14, Type = DUAL/GCLK, Sch name = GCLK1
#
## Leds
#NET "led_reset" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
#NET "Led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
#NET "led_mem" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
#NET "led_rw" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
#NET "Led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4
#NET "Led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5
#NET "Led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6
#NET "Led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7
## Switches
NET "sw<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
NET "sw<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
NET "sw<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
NET "sw<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
NET "sw<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
NET "sw<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
NET "sw<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
NET "sw<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
## Buttons
#NET "btn0" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
#NET "btn<1>" LOC = "D18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = BTN1
#NET "btn<2>" LOC = "E18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN2
#NET "btn<3>" LOC = "H13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN3
### 7 segment display
NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
## VGA Connector
NET "rgb<7>" LOC = "R9"; # Bank = 2, Pin name = IO/D5, Type = DUAL, Sch name = RED0
NET "rgb<6>" LOC = "T8"; # Bank = 2, Pin name = IO_L10N_2, Type = I/O, Sch name = RED1
NET "rgb<5>" LOC = "R8"; # Bank = 2, Pin name = IO_L10P_2, Type = I/O, Sch name = RED2
NET "rgb<4>" LOC = "N8"; # Bank = 2, Pin name = IO_L09N_2, Type = I/O, Sch name = GRN0
NET "rgb<3>" LOC = "P8"; # Bank = 2, Pin name = IO_L09P_2, Type = I/O, Sch name = GRN1
NET "rgb<2>" LOC = "P6"; # Bank = 2, Pin name = IO_L05N_2, Type = I/O, Sch name = GRN2
NET "rgb<1>" LOC = "U5"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = BLU1
NET "rgb<0>" LOC = "U4"; # Bank = 2, Pin name = IO_L03P_2/DOUT/BUSY, Type = DUAL, Sch name = BLU2
NET "Hs_out" LOC = "T4"; # Bank = 2, Pin name = IO_L03N_2/MOSI/CSI_B, Type = DUAL, Sch name = HSYNC
NET "Vs_out" LOC = "U3"; # Bank = 2, Pin name = IO_L01P_2/CSO_B, Type = DUAL, Sch name = VSYNC
## RS232 connector
#NET "RsRx" LOC = "U6"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = RS-RX
NET "btwn" LOC = "P9"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = RS-TX
## PS/2 connector
NET "ps2_clk" LOC = "R12"; # Bank = 2, Pin name = IO_L20N_2, Type = I/O, Sch name = PS2C
NET "ps2_data" LOC = "P11"; # Bank = 2, Pin name = IO_L18P_2, Type = I/O, Sch name = PS2D
## onBoard Cellular RAM and StrataFlash
#NET "MemOE" LOC = "T2"; # Bank = 3, Pin name = IO_L24P_3, Type = I/O, Sch name = OE
#NET "MemWR" LOC = "N7"; # Bank = 2, Pin name = IO_L07P_2, Type = I/O, Sch name = WE
#
#NET "RamAdv" LOC = "J4"; # Bank = 3, Pin name = IO_L11N_3/LHCLK1, Type = LHCLK, Sch name = MT-ADV
#NET "RamCS" LOC = "R6"; # Bank = 2, Pin name = IO_L05P_2, Type = I/O, Sch name = MT-CE
#NET "RamClk" LOC = "H5"; # Bank = 3, Pin name = IO_L08N_3, Type = I/O, Sch name = MT-CLK
#NET "RamCRE" LOC = "P7"; # Bank = 2, Pin name = IO_L07N_2, Type = I/O, Sch name = MT-CRE
#NET "RamLB" LOC = "K5"; # Bank = 3, Pin name = IO_L14N_3/LHCLK7, Type = LHCLK, Sch name = MT-LB
#NET "RamUB" LOC = "K4"; # Bank = 3, Pin name = IO_L13N_3/LHCLK5, Type = LHCLK, Sch name = MT-UB
#NET "RamWait" LOC = "F5"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = MT-WAIT
#NET "FlashRp" LOC = "T5"; # Bank = 2, Pin name = IO_L04N_2, Type = I/O, Sch name = RP#
#NET "FlashCS" LOC = "R5"; # Bank = 2, Pin name = IO_L04P_2, Type = I/O, Sch name = ST-CE
#NET "FlashStSts" LOC = "D3"; # Bank = 3, Pin name = IP, Type = INPUT, Sch name = ST-STS
#NET "MemAdr<1>" LOC = "J1"; # Bank = 3, Pin name = IO_L12P_3/LHCLK2, Type = LHCLK, Sch name = ADR1
#NET "MemAdr<2>" LOC = "J2"; # Bank = 3, Pin name = IO_L12N_3/LHCLK3/IRDY2, Type = LHCLK, Sch name = ADR2
#NET "MemAdr<3>" LOC = "H4"; # Bank = 3, Pin name = IO_L09P_3, Type = I/O, Sch name = ADR3
#NET "MemAdr<4>" LOC = "H1"; # Bank = 3, Pin name = IO_L10N_3, Type = I/O, Sch name = ADR4
#NET "MemAdr<5>" LOC = "H2"; # Bank = 3, Pin name = IO_L10P_3, Type = I/O, Sch name = ADR5
#NET "MemAdr<6>" LOC = "J5"; # Bank = 3, Pin name = IO_L11P_3/LHCLK0, Type = LHCLK, Sch name = ADR6
#NET "MemAdr<7>" LOC = "H3"; # Bank = 3, Pin name = IO_L09N_3, Type = I/O, Sch name = ADR7
#NET "MemAdr<8>" LOC = "H6"; # Bank = 3, Pin name = IO_L08P_3, Type = I/O, Sch name = ADR8
#NET "MemAdr<9>" LOC = "F1"; # Bank = 3, Pin name = IO_L05P_3, Type = I/O, Sch name = ADR9
#NET "MemAdr<10>" LOC = "G3"; # Bank = 3, Pin name = IO_L06P_3, Type = I/O, Sch name = ADR10
#NET "MemAdr<11>" LOC = "G6"; # Bank = 3, Pin name = IO_L07P_3, Type = I/O, Sch name = ADR11
#NET "MemAdr<12>" LOC = "G5"; # Bank = 3, Pin name = IO_L07N_3, Type = I/O, Sch name = ADR12
#NET "MemAdr<13>" LOC = "G4"; # Bank = 3, Pin name = IO_L06N_3/VREF_3, Type = VREF, Sch name = ADR13
#NET "MemAdr<14>" LOC = "F2"; # Bank = 3, Pin name = IO_L05N_3, Type = I/O, Sch name = ADR14
#NET "MemAdr<15>" LOC = "E1"; # Bank = 3, Pin name = IO_L03N_3, Type = I/O, Sch name = ADR15
#NET "MemAdr<16>" LOC = "M5"; # Bank = 3, Pin name = IO_L19P_3, Type = I/O, Sch name = ADR16
#NET "MemAdr<17>" LOC = "E2"; # Bank = 3, Pin name = IO_L03P_3, Type = I/O, Sch name = ADR17
#NET "MemAdr<18>" LOC = "C2"; # Bank = 3, Pin name = IO_L01N_3, Type = I/O, Sch name = ADR18
#NET "MemAdr<19>" LOC = "C1"; # Bank = 3, Pin name = IO_L01P_3, Type = I/O, Sch name = ADR19
#NET "MemAdr<20>" LOC = "D2"; # Bank = 3, Pin name = IO_L02N_3/VREF_3, Type = VREF, Sch name = ADR20
#NET "MemAdr<21>" LOC = "K3"; # Bank = 3, Pin name = IO_L13P_3/LHCLK4/TRDY2, Type = LHCLK, Sch name = ADR21
#NET "MemAdr<22>" LOC = "D1"; # Bank = 3, Pin name = IO_L02P_3, Type = I/O, Sch name = ADR22
#NET "MemAdr<23>" LOC = "K6"; # Bank = 3, Pin name = IO_L14P_3/LHCLK6, Type = LHCLK, Sch name = ADR23
#
#NET "MemDB<0>" LOC = "L1"; # Bank = 3, Pin name = IO_L15P_3, Type = I/O, Sch name = DB0
#NET "MemDB<1>" LOC = "L4"; # Bank = 3, Pin name = IO_L16N_3, Type = I/O, Sch name = DB1
#NET "MemDB<2>" LOC = "L6"; # Bank = 3, Pin name = IO_L17P_3, Type = I/O, Sch name = DB2
#NET "MemDB<3>" LOC = "M4"; # Bank = 3, Pin name = IO_L18P_3, Type = I/O, Sch name = DB3
#NET "MemDB<4>" LOC = "N5"; # Bank = 3, Pin name = IO_L20N_3, Type = I/O, Sch name = DB4
#NET "MemDB<5>" LOC = "P1"; # Bank = 3, Pin name = IO_L21N_3, Type = I/O, Sch name = DB5
#NET "MemDB<6>" LOC = "P2"; # Bank = 3, Pin name = IO_L21P_3, Type = I/O, Sch name = DB6
#NET "MemDB<7>" LOC = "R2"; # Bank = 3, Pin name = IO_L23N_3, Type = I/O, Sch name = DB7
#NET "MemDB<8>" LOC = "L3"; # Bank = 3, Pin name = IO_L16P_3, Type = I/O, Sch name = DB8
#NET "MemDB<9>" LOC = "L5"; # Bank = 3, Pin name = IO_L17N_3/VREF_3, Type = VREF, Sch name = DB9
#NET "MemDB<10>" LOC = "M3"; # Bank = 3, Pin name = IO_L18N_3, Type = I/O, Sch name = DB10
#NET "MemDB<11>" LOC = "M6"; # Bank = 3, Pin name = IO_L19N_3, Type = I/O, Sch name = DB11
#NET "MemDB<12>" LOC = "L2"; # Bank = 3, Pin name = IO_L15N_3, Type = I/O, Sch name = DB12
#NET "MemDB<13>" LOC = "N4"; # Bank = 3, Pin name = IO_L20P_3, Type = I/O, Sch name = DB13
#NET "MemDB<14>" LOC = "R3"; # Bank = 3, Pin name = IO_L23P_3, Type = I/O, Sch name = DB14
#NET "MemDB<15>" LOC = "T1"; # Bank = 3, Pin name = IO_L24N_3, Type = I/O, Sch name = DB15
## FX2 connector
#NET "PIO<0>" LOC = "B4"; # Bank = 0, Pin name = IO_L24N_0, Type = I/O, Sch name = R-IO1
#NET "PIO<1>" LOC = "A4"; # Bank = 0, Pin name = IO_L24P_0, Type = I/O, Sch name = R-IO2
#NET "PIO<2>" LOC = "C3"; # Bank = 0, Pin name = IO_L25P_0, Type = I/O, Sch name = R-IO3
#NET "PIO<3>" LOC = "C4"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO4
#NET "PIO<4>" LOC = "B6"; # Bank = 0, Pin name = IO_L20P_0, Type = I/O, Sch name = R-IO5
#NET "PIO<5>" LOC = "D5"; # Bank = 0, Pin name = IO_L23N_0/VREF_0, Type = VREF, Sch name = R-IO6
#NET "PIO<6>" LOC = "C5"; # Bank = 0, Pin name = IO_L23P_0, Type = I/O, Sch name = R-IO7
#NET "PIO<7>" LOC = "F7"; # Bank = 0, Pin name = IO_L19P_0, Type = I/O, Sch name = R-IO8
#NET "PIO<8>" LOC = "E7"; # Bank = 0, Pin name = IO_L19N_0/VREF_0, Type = VREF, Sch name = R-IO9
#NET "PIO<9>" LOC = "A6"; # Bank = 0, Pin name = IO_L20N_0, Type = I/O, Sch name = R-IO10
#NET "PIO<10>" LOC = "C7"; # Bank = 0, Pin name = IO_L18P_0, Type = I/O, Sch name = R-IO11
#NET "PIO<11>" LOC = "F8"; # Bank = 0, Pin name = IO_L17N_0, Type = I/O, Sch name = R-IO12
#NET "PIO<12>" LOC = "D7"; # Bank = 0, Pin name = IO_L18N_0/VREF_0, Type = VREF, Sch name = R-IO13
#NET "PIO<13>" LOC = "E8"; # Bank = 0, Pin name = IO_L17P_0, Type = I/O, Sch name = R-IO14
#NET "PIO<14>" LOC = "E9"; # Bank = 0, Pin name = IO_L15P_0, Type = I/O, Sch name = R-IO15
#NET "PIO<15>" LOC = "C9"; # Bank = 0, Pin name = IO_L14P_0/GCLK10, Type = GCLK, Sch name = R-IO16
#NET "PIO<16>" LOC = "A8"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO17
#NET "PIO<17>" LOC = "G9"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO18
#NET "PIO<18>" LOC = "F9"; # Bank = 0, Pin name = IO_L15N_0, Type = I/O, Sch name = R-IO19
#NET "PIO<19>" LOC = "D10"; # Bank = 0, Pin name = IO_L11P_0/GCLK4, Type = GCLK, Sch name = R-IO20
#NET "PIO<20>" LOC = "A10"; # Bank = 0, Pin name = IO_L12N_0/GCLK7, Type = GCLK, Sch name = R-IO21
#NET "PIO<21>" LOC = "B10"; # Bank = 0, Pin name = IO_L12P_0/GCLK6, Type = GCLK, Sch name = R-IO22
#NET "PIO<22>" LOC = "A11"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO23
#NET "PIO<23>" LOC = "D11"; # Bank = 0, Pin name = IO_L09N_0, Type = I/O, Sch name = R-IO24
#NET "PIO<24>" LOC = "E10"; # Bank = 0, Pin name = IO_L11N_0/GCLK5, Type = GCLK, Sch name = R-IO25
#NET "PIO<25>" LOC = "B11"; # Bank = 0, Pin name = IO/VREF_0, Type = VREF, Sch name = R-IO26
#NET "PIO<26>" LOC = "C11"; # Bank = 0, Pin name = IO_L09P_0, Type = I/O, Sch name = R-IO27
#NET "PIO<27>" LOC = "E11"; # Bank = 0, Pin name = IO_L08P_0, Type = I/O, Sch name = R-IO28
#NET "PIO<28>" LOC = "F11"; # Bank = 0, Pin name = IO_L08N_0, Type = I/O, Sch name = R-IO29
#NET "PIO<29>" LOC = "E12"; # Bank = 0, Pin name = IO_L06N_0, Type = I/O, Sch name = R-IO30
#NET "PIO<30>" LOC = "F12"; # Bank = 0, Pin name = IO_L06P_0, Type = I/O, Sch name = R-IO31
#NET "PIO<31>" LOC = "A13"; # Bank = 0, Pin name = IO_L05P_0, Type = I/O, Sch name = R-IO32
#NET "PIO<32>" LOC = "B13"; # Bank = 0, Pin name = IO_L05N_0/VREF_0, Type = VREF, Sch name = R-IO33
#NET "PIO<33>" LOC = "E13"; # Bank = 0, Pin name = IO, Type = I/O, Sch name = R-IO34
#NET "PIO<34>" LOC = "A14"; # Bank = 0, Pin name = IO_L04N_0, Type = I/O, Sch name = R-IO35
#NET "PIO<35>" LOC = "C14"; # Bank = 0, Pin name = IO_L03N_0/VREF_0, Type = VREF, Sch name = R-IO36
#NET "PIO<36>" LOC = "D14"; # Bank = 0, Pin name = IO_L03P_0, Type = I/O, Sch name = R-IO37
#NET "PIO<37>" LOC = "B14"; # Bank = 0, Pin name = IO_L04P_0, Type = I/O, Sch name = R-IO38
#NET "PIO<38>" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
#NET "PIO<39>" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
## 12 pin connectors
#NET "JA<0>" LOC = "L15"; # Bank = 1, Pin name = IO_L09N_1/A11, Type = DUAL, Sch name = JA1
#NET "JA<1>" LOC = "K12"; # Bank = 1, Pin name = IO_L11N_1/A9/RHCLK1, Type = RHCLK/DUAL, Sch name = JA2
#NET "JA<2>" LOC = "L17"; # Bank = 1, Pin name = IO_L10N_1/VREF_1, Type = VREF, Sch name = JA3
#NET "JA<3>" LOC = "M15"; # Bank = 1, Pin name = IO_L07P_1, Type = I/O, Sch name = JA4
#NET "JA<4>" LOC = "K13"; # Bank = 1, Pin name = IO_L11P_1/A10/RHCLK0, Type = RHCLK/DUAL, Sch name = JA7
#NET "JA<5>" LOC = "L16"; # Bank = 1, Pin name = IO_L09P_1/A12, Type = DUAL, Sch name = JA8
#NET "JA<6>" LOC = "M14"; # Bank = 1, Pin name = IO_L05P_1, Type = I/O, Sch name = JA9
#NET "JA<7>" LOC = "M16"; # Bank = 1, Pin name = IO_L07N_1, Type = I/O, Sch name = JA10
#NET "JB<0>" LOC = "M13"; # Bank = 1, Pin name = IO_L05N_1/VREF_1, Type = VREF, Sch name = JB1
#NET "JB<1>" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
#NET "JB<2>" LOC = "R15"; # Bank = 1, Pin name = IO_L03P_1, Type = I/O, Sch name = JB3
#NET "JB<3>" LOC = "T17"; # Bank = 1, Pin name = IO_L01N_1/A15, Type = DUAL, Sch name = JB4
#NET "JB<4>" LOC = "P17"; # Bank = 1, Pin name = IO_L06P_1, Type = I/O, Sch name = JB7
#NET "JB<5>" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
#NET "JB<6>" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
#NET "JB<7>" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
#NET "JC<0>" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
#NET "JC<1>" LOC = "J16"; # Bank = 1, Pin name = IO_L13N_1/A5/RHCLK5, Type = RHCLK/DUAL, Sch name = JC2
#NET "JC<2>" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
#NET "JC<3>" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
#NET "JC<4>" LOC = "H15"; # Bank = 1, Pin name = IO_L17N_1, Type = I/O, Sch name = JC7
#NET "JC<5>" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
#NET "JC<6>" LOC = "G16"; # Bank = 1, Pin name = IO_L18N_1, Type = I/O, Sch name = JC9
#NET "JC<7>" LOC = "J12"; # Bank = 1, Pin name = IO_L15P_1/A2, Type = DUAL, Sch name = JC10
#NET "JD<0>" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
#NET "JD<1>" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
## onBoard USB controller
#NET "EppAstb" LOC = "V14"; # Bank = 2, Pin name = IP_L23P_2, Type = INPUT, Sch name = U-FLAGA
#NET "EppDstb" LOC = "U14"; # Bank = 2, Pin name = IP_L23N_2, Type = INPUT, Sch name = U-FLAGB
#NET "UsbFlag" LOC = "V16"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-FLAGC
#NET "EppWait" LOC = "N9"; # Bank = 2, Pin name = IO_L12P_2/D7/GCLK12, Type = DUAL/GCLK, Sch name = U-SLRD
#NET "EppDB<0>" LOC = "R14"; # Bank = 2, Pin name = IO_L24N_2/A20, Type = DUAL, Sch name = U-FD0
#NET "EppDB<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L22N_2/A22, Type = DUAL, Sch name = U-FD1
#NET "EppDB<2>" LOC = "P13"; # Bank = 2, Pin name = IO_L22P_2/A23, Type = DUAL, Sch name = U-FD2
#NET "EppDB<3>" LOC = "T12"; # Bank = 2, Pin name = IO_L20P_2, Type = I/O, Sch name = U-FD3
#NET "EppDB<4>" LOC = "N11"; # Bank = 2, Pin name = IO_L18N_2, Type = I/O, Sch name = U-FD4
#NET "EppDB<5>" LOC = "R11"; # Bank = 2, Pin name = IO, Type = I/O, Sch name = U-FD5
#NET "EppDB<6>" LOC = "P10"; # Bank = 2, Pin name = IO_L15N_2/D1/GCLK3, Type = DUAL/GCLK, Sch name = U-FD6
#NET "EppDB<7>" LOC = "R10"; # Bank = 2, Pin name = IO_L15P_2/D2/GCLK2, Type = DUAL/GCLK, Sch name = U-FD7
#NET "UsbClk" LOC = "T15"; # Bank = 2, Pin name = IO/VREF_2, Type = VREF, Sch name = U-IFCLK
#NET "UsbOE" LOC = "V15"; # Bank = 2, Pin name = IO_L25P_2/VS2/A19, Type = DUAL, Sch name = U-SLOE
#NET "UsbWR" LOC = "V9"; # Bank = 2, Pin name = IO_L13N_2/D3/GCLK15, Type = DUAL/GCLK, Sch name = U-SWLR
#NET "UsbPktEnd" LOC = "V12"; # Bank = 2, Pin name = IO_L19P_2, Type = I/O, Sch name = U-PKTEND
#NET "UsbDir" LOC = "T16"; # Bank = 2, Pin name = IO_L26P_2/VS0/A17, Type = DUAL, Sch name = U-SLCS
#NET "UsbMode" LOC = "U15"; # Bank = 2, Pin name = IO_L25N_2/VS1/A18, Type = DUAL, Sch name = U-INT0#
#NET "UsbAdr<0>" LOC = "T14"; # Bank = 2, Pin name = IO_L24P_2/A21, Type = DUAL, Sch name = U-FIFOAD0
#NET "UsbAdr<1>" LOC = "V13"; # Bank = 2, Pin name = IO_L19N_2/VREF_2, Type = VREF, Sch name = U-FIFOAD1
##NET "UsbRdy" LOC = "U13"; # Bank = 2, Pin name = IP, Type = INPUT, Sch name = U-RDY

BIN
ecen320/tx_encoder/Tx.bit Normal file
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76
ecen320/tx_encoder/charGen.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity charGen is
port(
clk: in std_logic;
char_we: in std_logic;
char_value: in std_logic_vector(7 downto 0);
char_addr: in std_logic_vector(11 downto 0);
pixel_x, pixel_y: in std_logic_vector(9 downto 0);
pixel_out: out std_logic
);
end charGen;
architecture charGen_arch of charGen is
component char_mem
port(
clk: in std_logic;
char_read_addr : in std_logic_vector(11 downto 0);
char_write_addr: in std_logic_vector(11 downto 0);
char_we : in std_logic;
char_write_value : in std_logic_vector(7 downto 0);
char_read_value : out std_logic_vector(7 downto 0)
);
end component;
component font_rom
port(
clk: in std_logic;
addr: in std_logic_vector(10 downto 0);
data: out std_logic_vector(7 downto 0)
);
end component;
signal rom_addr: std_logic_vector(10 downto 0);
signal ram_read_addr: std_logic_vector(11 downto 0);
signal ram_value: std_logic_vector(7 downto 0);
signal myselect: std_logic_vector(2 downto 0);
signal tempvar: std_logic_vector(2 downto 0);
signal rom_data_out: std_logic_vector(7 downto 0);
begin
myRam: char_mem
port map(clk=>clk, char_read_addr=>ram_read_addr, char_write_addr=>char_addr, char_we=>char_we, char_write_value=>char_value, char_read_value=>ram_value
);
myRom: font_rom
port map(clk=>clk, addr=>rom_addr, data=>rom_data_out
);
process(clk)
begin
if(rising_edge(clk)) then
tempvar <= pixel_x(2 downto 0);
myselect <= tempvar;
end if;
end process;
with myselect select
pixel_out <= rom_data_out(7) when "000",
rom_data_out(6) when "001",
rom_data_out(5) when "010",
rom_data_out(4) when "011",
rom_data_out(3) when "100",
rom_data_out(2) when "101",
rom_data_out(1) when "110",
rom_data_out(0) when others;
ram_read_addr <= pixel_y(8 downto 4) & pixel_x(9 downto 3);
rom_addr <= ram_value(6 downto 0) & pixel_y(3 downto 0);
end charGen_arch;

228
ecen320/tx_encoder/charGen_toplevel.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity charGen_toplevel is
port(
clk: in std_logic;
rgb: out std_logic_vector(7 downto 0);
hs_out, vs_out: out std_logic;
sw: in std_logic_vector(7 downto 0);
seg : out std_logic_vector(6 downto 0);
an : out std_logic_vector(3 downto 0) := "1100";
dp : out std_logic;
btn: in std_logic_vector(3 downto 0);
ps2_clk : IN STD_LOGIC; --clock signal from PS2 keyboard
ps2_data : IN STD_LOGIC;
btwn: out std_logic
);
end charGen_toplevel;
architecture top_charGen of charGen_toplevel is
component ps2_keyboard_to_ascii is
generic(
clk_freq : INTEGER := 50_000_000; --system clock frequency in Hz
ps2_debounce_counter_size : INTEGER := 8 --set such that 2^size/clk_freq = 5us (size = 8 for 50MHz)
);
port(
clk : IN STD_LOGIC; --system clock input
ps2_clk : IN STD_LOGIC; --clock signal from PS2 keyboard
ps2_data : IN STD_LOGIC; --data signal from PS2 keyboard
ascii_code : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
ascii_new : OUT STD_LOGIC
);
end component;
component charGen is
port(
clk: in std_logic;
char_we: in std_logic;
char_value: in std_logic_vector(7 downto 0);
char_addr: in std_logic_vector(11 downto 0);
pixel_x: in std_logic_vector(9 downto 0);
pixel_y: in std_logic_vector(9 downto 0);
pixel_out: out std_logic
);
end component;
component vga_timing is
port(
clk, rst: in std_logic;
HS: out std_logic;
VS: out std_logic;
pixel_x, pixel_y: out std_logic_vector(9 downto 0);
last_column, last_row: out std_logic;
blank: out std_logic
);
end component;
component seven_segment_display is
generic(
COUNT: natural := 15
);
port(
clk: in std_logic;
data_in: in std_logic_vector(15 downto 0);
dp_in: in std_logic_Vector(3 downto 0);
blank: in std_logic_vector(3 downto 0);
seg : out std_logic_vector(6 downto 0);
dp : out std_logic;
an : out std_logic_vector(3 downto 0)
);
end component;
component tx is
generic(
CLK_RATE: natural := 50_000_000;
BAUD_RATE: natural := 19_200
);
port(
clk: in std_logic;
rst: in std_logic;
data_in: in std_logic_vector(7 downto 0);
send_character: in std_logic;
tx_out: out std_logic;
tx_busy:out std_logic
);
end component;
signal temp_x,temp_y: std_logic_vector(9 downto 0);
signal hs,vs: std_logic;
signal temp_hs,temp_vs: std_logic := '0';
signal reset: std_logic := '0';
signal dp_in: std_logic_vector(3 downto 0) := "0000";
signal blank4: std_logic_vector(3 downto 0) := (others=>'0');
signal data_in: std_logic_vector(15 downto 0) := (others=>'0');
signal data_in123: std_logic_vector(7 downto 0) := (others=>'0');
signal pixel_out: std_logic;
signal count: natural := 0;
signal count_next: natural;
signal count_en: std_logic;
signal count_key: natural := 0;
signal count_next_key: natural;
signal count_en_key: std_logic;
signal count_en_start: std_logic;
signal char_we: std_logic;
signal row_position, column_position: natural := 0;
signal row_next, column_next: natural;
signal row_en: std_logic;
signal char_write_addr: std_logic_vector(11 downto 0) := (others=>'0');
signal blank: std_logic := '0';
signal font_color: std_logic_vector(7 downto 0) := (others=>'1');
signal back_color: std_logic_vector(7 downto 0) := (others => '0');
signal ascii_new_temp : STD_LOGIC; --output flag indicating new ASCII value
signal ascii_code_temp : STD_LOGIC_VECTOR(6 DOWNTO 0); --ASCII value
signal ascii_code_buf : Std_logic_vector(7 downto 0);
signal go : std_logic:='0';
signal tx_out : std_logic;
signal tx_busy: std_logic;
begin
bottom_tx: tx
port map(clk=>clk, rst=>reset, send_character=>ascii_new_temp,
tx_out=>tx_out, tx_busy=>tx_busy, data_in=>data_in123
);
bottom_ps2: ps2_keyboard_to_ascii
port map(clk=>clk,ps2_clk=>ps2_clk,ps2_data=>ps2_data,ascii_new=>ascii_new_temp,ascii_code=>ascii_code_temp
);
bottom_level: vga_timing
port map(clk=>clk, rst=>reset, pixel_x=>temp_x, pixel_y=>temp_y, blank=>blank,
HS=>hs, VS=>vs, last_column=>open, last_row=>open
);
bottom_charGen: charGen
port map(clk=>clk, char_we=>char_we, char_value=>ascii_code_buf, char_addr=>char_write_addr, pixel_x=>temp_x, pixel_y=>temp_y, pixel_out=>pixel_out
);
bottom_segment: seven_segment_display
generic map(COUNT=>15)
port map(clk=>clk, an=>an, seg=>seg, dp=>dp, blank=>blank4,
data_in=>data_in, dp_in=>dp_in
);
ascii_code_buf <= "0" & ascii_code_temp;
data_in <= "000000000" & ascii_code_temp;
data_in123 <= std_logic_vector(unsigned("0" & ascii_code_temp) + unsigned(sw));
-- DELAY for char_gen
process(clk)
begin
if(rising_edge(clk)) then
count <= count_next;
end if;
end process;
count_next <= 0 when count=3000000 else
count + 1;
count_en <= '1' when count=3000000 else
'0';
-- ROW AND COL LOGIC
row_next <= row_position+1 when row_position < 30 else
0;
column_next <= column_position+1 when column_position < 79 else
0;
row_en <= '1' when column_position = 79 else
'0';
char_write_addr <= std_logic_vector(to_unsigned(row_position,5)) & std_logic_vector(to_unsigned(column_position,7));
font_color <= sw;
back_color <= not sw;
-- COLOR
rgb <= std_logic_vector(font_color) when pixel_out='1' else
std_logic_vector(back_color) when blank = '0' else
"00000000";
btwn <= tx_out;
process(clk)
begin
if(rising_edge(clk)) then
if(ascii_new_temp = '1') then
go <='1';
end if;
if(char_we = '1') then
go <='0';
end if;
end if;
end process;
-- BUTTON
char_we <= '1' when count_en = '1' and go = '1' else '0';
process(clk,ascii_new_temp,count_en)
begin
if(rising_edge(clk)) then
if (btn(3)='1') then
reset <= '1';
column_position <= 0;
row_position <= 0;
elsif (go = '1') then
if(count_en='1') then
reset <= '0';
column_position <= column_next;
if(row_en='1') then
row_position <= row_next;
end if;
end if;
else
reset <= '0';
end if;
end if;
end process;
-- DELAYS
process(clk,hs,vs)
begin
if(rising_edge(clk)) then
temp_hs <= hs;
temp_vs <= vs;
hs_out <= temp_hs;
vs_out <= temp_vs;
end if;
end process;
end top_charGen;

341
ecen320/tx_encoder/char_mem.vhd Normal file
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-- VGA Character Memory
--
-- This memory can store 128x32 characters where each character is
-- 8 bits. The memory is dual ported providing a port
-- to read the characters and a port to write the characters.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity char_mem is
port(
clk: in std_logic;
char_read_addr : in std_logic_vector(11 downto 0);
char_write_addr: in std_logic_vector(11 downto 0);
char_we : in std_logic;
char_write_value : in std_logic_vector(7 downto 0);
char_read_value : out std_logic_vector(7 downto 0)
);
end char_mem;
architecture arch of char_mem is
constant CHAR_RAM_ADDR_WIDTH: integer := 12; -- 2^7 X 2^5
constant CHAR_RAM_WIDTH: integer := 8; -- 8 bits per character
type char_ram_type is array (0 to 2**CHAR_RAM_ADDR_WIDTH-1)
of std_logic_vector(CHAR_RAM_WIDTH-1 downto 0);
signal read_a : std_logic_vector(11 downto 0);
-- character memory signal
signal char_ram : char_ram_type := (
-- Initial Value of character memory
-- Line 0
X"57",X"65",X"6c",X"63",X"6f",X"6d",X"65",X"20",X"74",X"6f",X"20",X"41",X"61",X"72",X"6f",X"6e",
X"20",X"61",X"6e",X"64",X"20",X"44",X"65",X"72",X"65",X"6b",X"27",X"73",X"20",X"65",X"6e",X"63",
X"72",X"79",X"70",X"74",X"69",X"6f",X"6e",X"20",X"70",X"72",X"6f",X"67",X"72",X"61",X"6d",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 1
X"49",X"6e",X"73",X"74",X"72",X"75",X"63",X"74",X"69",X"6f",X"6e",X"73",X"3a",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 2
X"2d",X"48",X"6f",X"6f",X"6b",X"20",X"75",X"70",X"20",X"61",X"6e",X"64",X"20",X"74",X"79",X"70",
X"65",X"20",X"69",X"6e",X"20",X"61",X"20",X"70",X"73",X"32",X"20",X"6b",X"65",X"79",X"62",X"6f",
X"61",X"72",X"64",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 3
X"2d",X"54",X"68",X"65",X"20",X"73",X"77",X"69",X"74",X"63",X"68",X"65",X"73",X"20",X"61",X"72",
X"65",X"20",X"74",X"68",X"65",X"20",X"6b",X"65",X"79",X"20",X"28",X"64",X"69",X"73",X"70",X"6c",
X"61",X"79",X"65",X"64",X"20",X"61",X"73",X"20",X"61",X"20",X"63",X"6f",X"6c",X"6f",X"72",X"20",
X"69",X"6e",X"20",X"74",X"68",X"65",X"20",X"62",X"61",X"63",X"6b",X"67",X"72",X"6f",X"75",X"6e",
X"64",X"29",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 4
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 5
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
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X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 21
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 22
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 23
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 24
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 25
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 26
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 27
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X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 28
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X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 29
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"54",--end of visible line
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 30
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X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- Line 31
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X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20"
);
begin
-- character memory concurrent statement
process(clk)
begin
if (clk'event and clk='1') then
if (char_we = '1') then
char_ram(to_integer(unsigned(char_write_addr))) <= char_write_value;
end if;
read_a <= char_read_addr;
end if;
end process;
char_read_value <= char_ram(to_integer(unsigned(read_a)));
end arch;

58
ecen320/tx_encoder/debounce.vhd Normal file
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@ -0,0 +1,58 @@
--------------------------------------------------------------------------------
--
-- FileName: debounce.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 3/26/2012 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY debounce IS
GENERIC(
counter_size : INTEGER := 25); --counter size (19 bits gives 10.5ms with 50MHz clock)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END debounce;
ARCHITECTURE logic OF debounce IS
SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set : STD_LOGIC; --sync reset to zero
SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
BEGIN
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops(0) <= button;
flipflops(1) <= flipflops(0);
If(counter_set = '1') THEN --reset counter because input is changing
counter_out <= (OTHERS => '0');
ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
counter_out <= counter_out + 1;
ELSE --stable input time is met
result <= flipflops(1);
END IF;
END IF;
END PROCESS;
END logic;

2215
ecen320/tx_encoder/font_rom.vhd Normal file
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108
ecen320/tx_encoder/ps2_keyboard.vhd Normal file
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@ -0,0 +1,108 @@
--------------------------------------------------------------------------------
--
-- FileName: ps2_keyboard.vhd
-- Dependencies: debounce.vhd
-- Design Software: Quartus II 32-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/25/2013 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ps2_keyboard IS
GENERIC(
clk_freq : INTEGER := 50_000_000; --system clock frequency in Hz
debounce_counter_size : INTEGER := 8); --set such that (2^size)/clk_freq = 5us (size = 8 for 50MHz)
PORT(
clk : IN STD_LOGIC; --system clock
ps2_clk : IN STD_LOGIC; --clock signal from PS/2 keyboard
ps2_data : IN STD_LOGIC; --data signal from PS/2 keyboard
ps2_code_new : OUT STD_LOGIC; --flag that new PS/2 code is available on ps2_code bus
ps2_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --code received from PS/2
END ps2_keyboard;
ARCHITECTURE logic OF ps2_keyboard IS
SIGNAL sync_ffs : STD_LOGIC_VECTOR(1 DOWNTO 0); --synchronizer flip-flops for PS/2 signals
SIGNAL ps2_clk_int : STD_LOGIC; --debounced clock signal from PS/2 keyboard
SIGNAL ps2_data_int : STD_LOGIC; --debounced data signal from PS/2 keyboard
SIGNAL ps2_word : STD_LOGIC_VECTOR(10 DOWNTO 0); --stores the ps2 data word
SIGNAL error : STD_LOGIC; --validate parity, start, and stop bits
SIGNAL count_idle : INTEGER RANGE 0 TO clk_freq/18_000; --counter to determine PS/2 is idle
--declare debounce component for debouncing PS2 input signals
COMPONENT debounce IS
GENERIC(
counter_size : INTEGER); --debounce period (in seconds) = 2^counter_size/(clk freq in Hz)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END COMPONENT;
BEGIN
--synchronizer flip-flops
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk = '1') THEN --rising edge of system clock
sync_ffs(0) <= ps2_clk; --synchronize PS/2 clock signal
sync_ffs(1) <= ps2_data; --synchronize PS/2 data signal
END IF;
END PROCESS;
--debounce PS2 input signals
debounce_ps2_clk: debounce
GENERIC MAP(counter_size => debounce_counter_size)
PORT MAP(clk => clk, button => sync_ffs(0), result => ps2_clk_int);
debounce_ps2_data: debounce
GENERIC MAP(counter_size => debounce_counter_size)
PORT MAP(clk => clk, button => sync_ffs(1), result => ps2_data_int);
--input PS2 data
PROCESS(ps2_clk_int)
BEGIN
IF(ps2_clk_int'EVENT AND ps2_clk_int = '0') THEN --falling edge of PS2 clock
ps2_word <= ps2_data_int & ps2_word(10 DOWNTO 1); --shift in PS2 data bit
END IF;
END PROCESS;
--verify that parity, start, and stop bits are all correct
error <= NOT (NOT ps2_word(0) AND ps2_word(10) AND (ps2_word(9) XOR ps2_word(8) XOR
ps2_word(7) XOR ps2_word(6) XOR ps2_word(5) XOR ps2_word(4) XOR ps2_word(3) XOR
ps2_word(2) XOR ps2_word(1)));
--determine if PS2 port is idle (i.e. last transaction is finished) and output result
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk = '1') THEN --rising edge of system clock
IF(ps2_clk_int = '0') THEN --low PS2 clock, PS/2 is active
count_idle <= 0; --reset idle counter
ELSIF(count_idle /= clk_freq/18_000) THEN --PS2 clock has been high less than a half clock period (<55us)
count_idle <= count_idle + 1; --continue counting
END IF;
IF(count_idle = clk_freq/18_000 AND error = '0') THEN --idle threshold reached and no errors detected
ps2_code_new <= '1'; --set flag that new PS/2 code is available
ps2_code <= ps2_word(8 DOWNTO 1); --output new PS/2 code
ELSE --PS/2 port active or error detected
ps2_code_new <= '0'; --set flag that PS/2 transaction is in progress
END IF;
END IF;
END PROCESS;
END logic;

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--------------------------------------------------------------------------------
--
-- FileName: ps2_keyboard_to_ascii.vhd
-- Dependencies: ps2_keyboard.vhd, debounce.vhd
-- Design Software: Quartus II 32-bit Version 12.1 Build 177 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/29/2013 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ps2_keyboard_to_ascii IS
GENERIC(
clk_freq : INTEGER := 50_000_000; --system clock frequency in Hz
ps2_debounce_counter_size : INTEGER := 8); --set such that 2^size/clk_freq = 5us (size = 8 for 50MHz)
PORT(
clk : IN STD_LOGIC; --system clock input
ps2_clk : IN STD_LOGIC; --clock signal from PS2 keyboard
ps2_data : IN STD_LOGIC; --data signal from PS2 keyboard
ascii_new : OUT STD_LOGIC; --output flag indicating new ASCII value
ascii_code : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); --ASCII value
END ps2_keyboard_to_ascii;
ARCHITECTURE behavior OF ps2_keyboard_to_ascii IS
TYPE machine IS(ready, new_code, translate, output); --needed states
SIGNAL state : machine; --state machine
SIGNAL ps2_code_new : STD_LOGIC; --new PS2 code flag from ps2_keyboard component
SIGNAL ps2_code : STD_LOGIC_VECTOR(7 DOWNTO 0); --PS2 code input form ps2_keyboard component
SIGNAL prev_ps2_code_new : STD_LOGIC := '1'; --value of ps2_code_new flag on previous clock
SIGNAL break : STD_LOGIC := '0'; --'1' for break code, '0' for make code
SIGNAL e0_code : STD_LOGIC := '0'; --'1' for multi-code commands, '0' for single code commands
SIGNAL caps_lock : STD_LOGIC := '0'; --'1' if caps lock is active, '0' if caps lock is inactive
SIGNAL control_r : STD_LOGIC := '0'; --'1' if right control key is held down, else '0'
SIGNAL control_l : STD_LOGIC := '0'; --'1' if left control key is held down, else '0'
SIGNAL shift_r : STD_LOGIC := '0'; --'1' if right shift is held down, else '0'
SIGNAL shift_l : STD_LOGIC := '0'; --'1' if left shift is held down, else '0'
SIGNAL ascii : STD_LOGIC_VECTOR(7 DOWNTO 0) := x"FF"; --internal value of ASCII translation
--declare PS2 keyboard interface component
COMPONENT ps2_keyboard IS
GENERIC(
clk_freq : INTEGER; --system clock frequency in Hz
debounce_counter_size : INTEGER); --set such that 2^size/clk_freq = 5us (size = 8 for 50MHz)
PORT(
clk : IN STD_LOGIC; --system clock
ps2_clk : IN STD_LOGIC; --clock signal from PS2 keyboard
ps2_data : IN STD_LOGIC; --data signal from PS2 keyboard
ps2_code_new : OUT STD_LOGIC; --flag that new PS/2 code is available on ps2_code bus
ps2_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --code received from PS/2
END COMPONENT;
BEGIN
--instantiate PS2 keyboard interface logic
ps2_keyboard_0: ps2_keyboard
GENERIC MAP(clk_freq => clk_freq, debounce_counter_size => ps2_debounce_counter_size)
PORT MAP(clk => clk, ps2_clk => ps2_clk, ps2_data => ps2_data, ps2_code_new => ps2_code_new, ps2_code => ps2_code);
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk = '1') THEN
prev_ps2_code_new <= ps2_code_new; --keep track of previous ps2_code_new values to determine low-to-high transitions
CASE state IS
--ready state: wait for a new PS2 code to be received
WHEN ready =>
IF(prev_ps2_code_new = '0' AND ps2_code_new = '1') THEN --new PS2 code received
ascii_new <= '0'; --reset new ASCII code indicator
state <= new_code; --proceed to new_code state
ELSE --no new PS2 code received yet
state <= ready; --remain in ready state
END IF;
--new_code state: determine what to do with the new PS2 code
WHEN new_code =>
IF(ps2_code = x"F0") THEN --code indicates that next command is break
break <= '1'; --set break flag
state <= ready; --return to ready state to await next PS2 code
ELSIF(ps2_code = x"E0") THEN --code indicates multi-key command
e0_code <= '1'; --set multi-code command flag
state <= ready; --return to ready state to await next PS2 code
ELSE --code is the last PS2 code in the make/break code
ascii(7) <= '1'; --set internal ascii value to unsupported code (for verification)
state <= translate; --proceed to translate state
END IF;
--translate state: translate PS2 code to ASCII value
WHEN translate =>
break <= '0'; --reset break flag
e0_code <= '0'; --reset multi-code command flag
--handle codes for control, shift, and caps lock
CASE ps2_code IS
WHEN x"58" => --caps lock code
IF(break = '0') THEN --if make command
caps_lock <= NOT caps_lock; --toggle caps lock
END IF;
WHEN x"14" => --code for the control keys
IF(e0_code = '1') THEN --code for right control
control_r <= NOT break; --update right control flag
ELSE --code for left control
control_l <= NOT break; --update left control flag
END IF;
WHEN x"12" => --left shift code
shift_l <= NOT break; --update left shift flag
WHEN x"59" => --right shift code
shift_r <= NOT break; --update right shift flag
WHEN OTHERS => NULL;
END CASE;
--translate control codes (these do not depend on shift or caps lock)
IF(control_l = '1' OR control_r = '1') THEN
CASE ps2_code IS
WHEN x"1E" => ascii <= x"00"; --^@ NUL
WHEN x"1C" => ascii <= x"01"; --^A SOH
WHEN x"32" => ascii <= x"02"; --^B STX
WHEN x"21" => ascii <= x"03"; --^C ETX
WHEN x"23" => ascii <= x"04"; --^D EOT
WHEN x"24" => ascii <= x"05"; --^E ENQ
WHEN x"2B" => ascii <= x"06"; --^F ACK
WHEN x"34" => ascii <= x"07"; --^G BEL
WHEN x"33" => ascii <= x"08"; --^H BS
WHEN x"43" => ascii <= x"09"; --^I HT
WHEN x"3B" => ascii <= x"0A"; --^J LF
WHEN x"42" => ascii <= x"0B"; --^K VT
WHEN x"4B" => ascii <= x"0C"; --^L FF
WHEN x"3A" => ascii <= x"0D"; --^M CR
WHEN x"31" => ascii <= x"0E"; --^N SO
WHEN x"44" => ascii <= x"0F"; --^O SI
WHEN x"4D" => ascii <= x"10"; --^P DLE
WHEN x"15" => ascii <= x"11"; --^Q DC1
WHEN x"2D" => ascii <= x"12"; --^R DC2
WHEN x"1B" => ascii <= x"13"; --^S DC3
WHEN x"2C" => ascii <= x"14"; --^T DC4
WHEN x"3C" => ascii <= x"15"; --^U NAK
WHEN x"2A" => ascii <= x"16"; --^V SYN
WHEN x"1D" => ascii <= x"17"; --^W ETB
WHEN x"22" => ascii <= x"18"; --^X CAN
WHEN x"35" => ascii <= x"19"; --^Y EM
WHEN x"1A" => ascii <= x"1A"; --^Z SUB
WHEN x"54" => ascii <= x"1B"; --^[ ESC
WHEN x"5D" => ascii <= x"1C"; --^\ FS
WHEN x"5B" => ascii <= x"1D"; --^] GS
WHEN x"36" => ascii <= x"1E"; --^^ RS
WHEN x"4E" => ascii <= x"1F"; --^_ US
WHEN x"4A" => ascii <= x"7F"; --^? DEL
WHEN OTHERS => NULL;
END CASE;
ELSE --if control keys are not pressed
--translate characters that do not depend on shift, or caps lock
CASE ps2_code IS
WHEN x"29" => ascii <= x"20"; --space
WHEN x"66" => ascii <= x"08"; --backspace (BS control code)
WHEN x"0D" => ascii <= x"09"; --tab (HT control code)
WHEN x"5A" => ascii <= x"0D"; --enter (CR control code)
WHEN x"76" => ascii <= x"1B"; --escape (ESC control code)
WHEN x"71" =>
IF(e0_code = '1') THEN --ps2 code for delete is a multi-key code
ascii <= x"7F"; --delete
END IF;
WHEN OTHERS => NULL;
END CASE;
--translate letters (these depend on both shift and caps lock)
IF((shift_r = '0' AND shift_l = '0' AND caps_lock = '0') OR
((shift_r = '1' OR shift_l = '1') AND caps_lock = '1')) THEN --letter is lowercase
CASE ps2_code IS
WHEN x"1C" => ascii <= x"61"; --a
WHEN x"32" => ascii <= x"62"; --b
WHEN x"21" => ascii <= x"63"; --c
WHEN x"23" => ascii <= x"64"; --d
WHEN x"24" => ascii <= x"65"; --e
WHEN x"2B" => ascii <= x"66"; --f
WHEN x"34" => ascii <= x"67"; --g
WHEN x"33" => ascii <= x"68"; --h
WHEN x"43" => ascii <= x"69"; --i
WHEN x"3B" => ascii <= x"6A"; --j
WHEN x"42" => ascii <= x"6B"; --k
WHEN x"4B" => ascii <= x"6C"; --l
WHEN x"3A" => ascii <= x"6D"; --m
WHEN x"31" => ascii <= x"6E"; --n
WHEN x"44" => ascii <= x"6F"; --o
WHEN x"4D" => ascii <= x"70"; --p
WHEN x"15" => ascii <= x"71"; --q
WHEN x"2D" => ascii <= x"72"; --r
WHEN x"1B" => ascii <= x"73"; --s
WHEN x"2C" => ascii <= x"74"; --t
WHEN x"3C" => ascii <= x"75"; --u
WHEN x"2A" => ascii <= x"76"; --v
WHEN x"1D" => ascii <= x"77"; --w
WHEN x"22" => ascii <= x"78"; --x
WHEN x"35" => ascii <= x"79"; --y
WHEN x"1A" => ascii <= x"7A"; --z
WHEN OTHERS => NULL;
END CASE;
ELSE --letter is uppercase
CASE ps2_code IS
WHEN x"1C" => ascii <= x"41"; --A
WHEN x"32" => ascii <= x"42"; --B
WHEN x"21" => ascii <= x"43"; --C
WHEN x"23" => ascii <= x"44"; --D
WHEN x"24" => ascii <= x"45"; --E
WHEN x"2B" => ascii <= x"46"; --F
WHEN x"34" => ascii <= x"47"; --G
WHEN x"33" => ascii <= x"48"; --H
WHEN x"43" => ascii <= x"49"; --I
WHEN x"3B" => ascii <= x"4A"; --J
WHEN x"42" => ascii <= x"4B"; --K
WHEN x"4B" => ascii <= x"4C"; --L
WHEN x"3A" => ascii <= x"4D"; --M
WHEN x"31" => ascii <= x"4E"; --N
WHEN x"44" => ascii <= x"4F"; --O
WHEN x"4D" => ascii <= x"50"; --P
WHEN x"15" => ascii <= x"51"; --Q
WHEN x"2D" => ascii <= x"52"; --R
WHEN x"1B" => ascii <= x"53"; --S
WHEN x"2C" => ascii <= x"54"; --T
WHEN x"3C" => ascii <= x"55"; --U
WHEN x"2A" => ascii <= x"56"; --V
WHEN x"1D" => ascii <= x"57"; --W
WHEN x"22" => ascii <= x"58"; --X
WHEN x"35" => ascii <= x"59"; --Y
WHEN x"1A" => ascii <= x"5A"; --Z
WHEN OTHERS => NULL;
END CASE;
END IF;
--translate numbers and symbols (these depend on shift but not caps lock)
IF(shift_l = '1' OR shift_r = '1') THEN --key's secondary character is desired
CASE ps2_code IS
WHEN x"16" => ascii <= x"21"; --!
WHEN x"52" => ascii <= x"22"; --"
WHEN x"26" => ascii <= x"23"; --#
WHEN x"25" => ascii <= x"24"; --$
WHEN x"2E" => ascii <= x"25"; --%
WHEN x"3D" => ascii <= x"26"; --&
WHEN x"46" => ascii <= x"28"; --(
WHEN x"45" => ascii <= x"29"; --)
WHEN x"3E" => ascii <= x"2A"; --*
WHEN x"55" => ascii <= x"2B"; --+
WHEN x"4C" => ascii <= x"3A"; --:
WHEN x"41" => ascii <= x"3C"; --<
WHEN x"49" => ascii <= x"3E"; -->
WHEN x"4A" => ascii <= x"3F"; --?
WHEN x"1E" => ascii <= x"40"; --@
WHEN x"36" => ascii <= x"5E"; --^
WHEN x"4E" => ascii <= x"5F"; --_
WHEN x"54" => ascii <= x"7B"; --{
WHEN x"5D" => ascii <= x"7C"; --|
WHEN x"5B" => ascii <= x"7D"; --}
WHEN x"0E" => ascii <= x"7E"; --~
WHEN OTHERS => NULL;
END CASE;
ELSE --key's primary character is desired
CASE ps2_code IS
WHEN x"45" => ascii <= x"30"; --0
WHEN x"16" => ascii <= x"31"; --1
WHEN x"1E" => ascii <= x"32"; --2
WHEN x"26" => ascii <= x"33"; --3
WHEN x"25" => ascii <= x"34"; --4
WHEN x"2E" => ascii <= x"35"; --5
WHEN x"36" => ascii <= x"36"; --6
WHEN x"3D" => ascii <= x"37"; --7
WHEN x"3E" => ascii <= x"38"; --8
WHEN x"46" => ascii <= x"39"; --9
WHEN x"52" => ascii <= x"27"; --'
WHEN x"41" => ascii <= x"2C"; --,
WHEN x"4E" => ascii <= x"2D"; ---
WHEN x"49" => ascii <= x"2E"; --.
WHEN x"4A" => ascii <= x"2F"; --/
WHEN x"4C" => ascii <= x"3B"; --;
WHEN x"55" => ascii <= x"3D"; --=
WHEN x"54" => ascii <= x"5B"; --[
WHEN x"5D" => ascii <= x"5C"; --\
WHEN x"5B" => ascii <= x"5D"; --]
WHEN x"0E" => ascii <= x"60"; --`
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
IF(break = '0') THEN --the code is a make
state <= output; --proceed to output state
ELSE --code is a break
state <= ready; --return to ready state to await next PS2 code
END IF;
--output state: verify the code is valid and output the ASCII value
WHEN output =>
IF(ascii(7) = '0') THEN --the PS2 code has an ASCII output
ascii_new <= '1'; --set flag indicating new ASCII output
ascii_code <= ascii(6 DOWNTO 0); --output the ASCII value
END IF;
state <= ready; --return to ready state to await next PS2 code
END CASE;
END IF;
END PROCESS;
END behavior;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity seven_segment_display is
generic(
COUNTER_BITS: natural := 15
);
port(
clk: in std_logic;
data_in: in std_logic_vector(15 downto 0);
dp_in: in std_logic_vector(3 downto 0);
blank: in std_logic_vector(3 downto 0);
seg: out std_logic_vector(6 downto 0);
dp: out std_logic;
an: out std_logic_vector(3 downto 0)
);
end seven_segment_display;
architecture seven_arch of seven_segment_display is
--signal which_sym: std_logic_vector(3 downto 0);
signal mydatain, an_temp: std_logic_vector(3 downto 0);
signal r_reg: unsigned(COUNTER_BITS-1 downto 0):=(others=>'0');
signal r_next: unsigned(COUNTER_BITS-1 downto 0);
signal anode_select: std_logic_vector(1 downto 0);
begin
--register
process(clk)
begin
if clk'event and clk='1' then
r_reg <= r_next;
end if;
end process;
--next-state logic
process(r_reg)
begin
r_next <= r_reg+1;
end process;
anode_select <= std_logic_vector(r_reg(COUNTER_BITS-1 downto COUNTER_BITS-2));
with mydatain select
seg <= "1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;
mydatain <= data_in(3 downto 0) when anode_select = "00" else
data_in(7 downto 4) when anode_select = "01" else
data_in(11 downto 8) when anode_select = "10" else
data_in(15 downto 12);
dp <= not dp_in(0) when anode_select="00" else
not dp_in(1) when anode_select="01" else
not dp_in(2) when anode_select="10" else
not dp_in(3);
an_temp <= "1110" when anode_select="00" else
"1101" when anode_select="01" else
"1011" when anode_select="10" else
"0111" when anode_select="11" else
"0000";
an <= an_temp or blank;
end seven_arch;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tx is
generic(
CLK_RATE: natural := 50_000_000;
BAUD_RATE: natural := 19_200
);
port(
clk: in std_logic;
rst: in std_logic;
data_in: in std_logic_vector(7 downto 0);
send_character: in std_logic;
tx_out: out std_logic;
tx_busy:out std_logic
);
end tx;
architecture tran_arch of tx is
function log2c(n: integer) return integer is
variable m, p: integer;
begin
m := 0;
p := 1;
while p<n loop
m:= m+1;
p:=p*2;
end loop;
return m;
end log2c;
constant BIT_COUNTER_MAX_VAL : Natural := CLK_RATE / BAUD_RATE - 1;
constant BIT_COUNTER_BITS : Natural := log2c(BIT_COUNTER_MAX_VAL);
signal counter: unsigned(BIT_COUNTER_BITS downto 0) := (others=>'0');
signal counter_next: unsigned(BIT_COUNTER_BITS downto 0);
type fsm_state_type is
(idle,strt,b0,b1,b2,b3,b4,b5,b6,b7,stp,retrn);
signal state_reg, state_next: fsm_state_type;
-- BitTimer signal
signal tx_bit: std_logic;
-- Shift Register signal
signal shift_out: std_logic;
signal shift_next: std_logic;
signal mydata: std_logic_vector(7 downto 0);
-- FSM signal
signal load: std_logic;
signal clrTimer: std_logic;
signal shift: std_logic;
signal stop: std_logic;
signal start: std_logic;
-- Transmit Out signal
begin
-- Transmit Out
process(clk,shift_out)
begin
if(clk'event and clk='1') then
tx_out <= shift_out;
if(start='1') then
tx_out <= '0';
end if;
if(stop='1') then
tx_out <= '1';
end if;
end if;
end process;
-- FSM
process(clk,rst)
begin
if(rst='1') then
state_reg <= idle;
elsif(clk'event and clk='1') then
state_reg <= state_next;
end if;
end process;
process(state_reg,send_character,tx_bit)
begin
state_next <= state_reg;
start <= '0';
stop <= '0';
tx_busy <= '1';
shift <= '0';
clrTimer <= '0';
load <= '0';
case state_reg is
when idle =>
stop <= '1';
clrTimer <= '1';
tx_busy <= '0';
if(send_character='1') then
load <= '1';
state_next <= strt;
end if;
when strt =>
start <= '1';
if(tx_bit='1') then
state_next <= b0;
end if;
when b0 =>
if(tx_bit='1') then
shift <= '1';
state_next <= b1;
end if;
when b1 =>
if(tx_bit='1') then
shift <= '1';
state_next <= b2;
end if;
when b2 =>
if(tx_bit='1') then
shift <= '1';
state_next <= b3;
end if;
when b3 =>
if(tx_bit='1') then
shift <= '1';
state_next <= b4;
end if;
when b4 =>
if(tx_bit='1') then
shift <= '1';
state_next <= b5;
end if;
when b5 =>
if(tx_bit='1') then
shift <= '1';
state_next <= b6;
end if;
when b6 =>
if(tx_bit='1') then
shift <= '1';
state_next <= b7;
end if;
when b7 =>
if(tx_bit='1') then
shift <= '1';
state_next <= stp;
end if;
when stp =>
stop <= '1';
if(tx_bit='1') then
state_next <= retrn;
end if;
when retrn =>
stop <= '1';
if(send_character='0') then
state_next <= idle;
end if;
end case;
end process;
-- BitTimer
process(clk,rst)
begin
if(rst='1') then
counter <= (others=>'0');
elsif(clk'event and clk='1') then
counter <= counter_next;
end if;
end process;
counter_next <= (others=>'0') when counter = to_unsigned(BIT_COUNTER_MAX_VAL,BIT_COUNTER_BITS) else
(others=>'0') when state_reg = idle else
counter+1;
tx_bit <= '1' when counter = to_unsigned(BIT_COUNTER_MAX_VAL,BIT_COUNTER_BITS) else
'0';
-- Shift Register
process(clk,rst,load)
begin
if(rst='1') then
mydata <= (others=>'0');
elsif(clk'event and clk='1') then
if(load = '1') then
mydata <= data_in;
else
mydata <= mydata;
end if;
shift_out <= shift_next;
end if;
end process;
shift_next <= mydata(0) when state_reg=b0 else
mydata(1) when state_reg=b1 else
mydata(2) when state_reg=b2 else
mydata(3) when state_reg=b3 else
mydata(4) when state_reg=b4 else
mydata(5) when state_reg=b5 else
mydata(6) when state_reg=b6 else
mydata(7) when state_reg=b7 else
'0';
end tran_arch;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tx_top is
generic(COUNTER_BIT: natural := 20);
port(
clk: in std_logic;
sw: in std_logic_vector(7 downto 0);
seg : out std_logic_vector(6 downto 0);
an : out std_logic_vector(3 downto 0) := "1100";
dp : out std_logic;
tx_out: out std_logic;
btn: in std_logic_vector(3 downto 0);
data_out : out std_logic_vector(15 downto 0)
);
end tx_top;
architecture top_arch of tx_top is
-- component seven_segment_display
-- generic(
-- COUNTER_BITS: natural := 15
-- );
-- port(
-- clk: in std_logic;
-- data_in: in std_logic_vector(15 downto 0);
-- dp_in: in std_logic_Vector(3 downto 0);
-- blank: in std_logic_vector(3 downto 0);
-- seg : out std_logic_vector(6 downto 0);
-- dp : out std_logic;
-- an : out std_logic_vector(3 downto 0)
-- );
-- end component;
component tx
port(
clk: in std_logic;
rst: in std_logic;
data_in: in std_logic_vector(7 downto 0);
send_character: in std_logic;
tx_out: out std_logic;
tx_busy: out std_logic
);
end component;
signal reset: std_logic := '0';
signal dp_in: std_logic_vector(3 downto 0) := "0000";
signal blank4: std_logic_vector(3 downto 0) := (others=>'0');
signal data_in: std_logic_vector(7 downto 0) := (others=>'0');
signal send_character: std_logic;
signal counter: unsigned(COUNTER_BIT downto 0) := (others=>'0');
signal debouncing: std_logic;
signal data_in2: std_logic_vector(15 downto 0) := (others=>'0');
begin
-- bottom_segment: seven_segment_display
-- generic map(COUNTER_BITS=>15)
-- port map(clk=>clk, an=>an, seg=>seg, dp=>dp, blank=>blank4,
-- data_in=>data_in2, dp_in=>dp_in
-- );
bottom_tx: tx
port map(clk=>clk, rst=>reset, send_character=>send_character,
tx_out=>tx_out, tx_busy=>open, data_in=>data_in
);
data_out <= "00000000" & sw;
data_in <= sw;
data_in2 <= "00000000" & sw;
-- debouncer
process(clk)
begin
if(rising_edge(clk)) then
if(counter = "111111111111111111111") then
debouncing <= '1';
counter <= (others=>'0');
else
debouncing <= '0';
counter <= counter+1;
end if;
end if;
end process;
-- button logic
process(clk,btn)
begin
if(rising_edge(clk)) then
if (btn(3)='1') then
reset <= '1';
elsif (btn(0)='1') then
if(debouncing='1') then
send_character <= '1';
end if;
else
reset <= '0';
send_character <= '0';
end if;
end if;
end process;
end top_arch;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_timing is
port(
clk: in std_logic;
rst: in std_logic;
HS: out std_logic;
VS: out std_logic;
pixel_x: out std_logic_vector(9 downto 0);
pixel_y: out std_logic_vector(9 downto 0);
last_column: out std_logic;
last_row: out std_logic;
blank: out std_logic
);
end vga_timing;
architecture behavior of vga_timing is
signal pixel_en: std_logic := '0';
signal column: unsigned(9 downto 0);
signal column_next: unsigned(9 downto 0);
signal row: unsigned(9 downto 0);
signal row_next: unsigned(9 downto 0);
begin
-- pixel clock
process(clk, rst)
begin
if(rst = '1') then
pixel_en <= '0';
elsif(clk'event and clk='1') then
pixel_en <= not pixel_en;
end if;
end process;
-- register for HS counter
process(rst,clk)
begin
if(rst = '1') then
column <= (others=>'0');
elsif(clk'event and clk = '1') then
if(pixel_en = '1') then
column <= column_next;
end if;
end if;
end process;
-- next state HS counter
column_next <= (others=>'0') when column = 799 else
column + 1;
-- output logic for HS counter
last_column <= '1' when column = 639 else
'0';
HS <= '0' when ((column > 655) and (column < 752)) else
'1';
pixel_x <= std_logic_vector(column);
-- register for VS counter
process(rst,clk, pixel_en, column)
begin
if(rst = '1') then
row <= (others=>'0');
elsif(clk'event and clk = '1') then
if(pixel_en = '1' and column = 799) then -- only increment if HS is 799 and the pixel enable is high
row <= row_next;
end if;
end if;
end process;
-- next state VS counter
row_next <= (others=>'0') when row = 520 else
row + 1;
-- output logic for VS counter
last_row <= '1' when row = 479 else
'0';
VS <= '0' when ((row > 489) and (row < 492)) else
'1';
pixel_y <= std_logic_vector(row);
-- blank signal
blank <= '1' when (row > 479) or (column > 639) else
'0';
end behavior;