78 lines
1.8 KiB
VHDL
78 lines
1.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vga_timing is
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port(
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clk, rst: in std_logic;
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HS, VS: out std_logic;
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pixel_x, pixel_y: out std_logic_vector(9 downto 0);
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last_column, last_row: out std_logic;
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blank: out std_logic
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);
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end vga_timing;
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architecture vga_arch of vga_timing is
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signal pixel_en: std_logic := '0';
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signal column: unsigned(9 downto 0) := (others=>'0');
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signal column_next: unsigned(9 downto 0);
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signal row_en: std_logic;
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signal row: unsigned(9 downto 0) := (others=>'0');
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signal row_next: unsigned(9 downto 0);
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begin
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-- pixel clock
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process(clk,rst)
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begin
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if(rst='1') then
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pixel_en <= '0';
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elsif(clk'event and clk='1') then
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pixel_en <= not pixel_en;
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end if;
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end process;
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-- horizontal counter
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process(pixel_en,rst)
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begin
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if(rst='1') then
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column <= (others=>'0');
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elsif(pixel_en'event and pixel_en='1') then
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column <= column_next;
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end if;
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end process;
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column_next <= (others=>'0') when column=799 else
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column + 1;
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row_en <= '1' when column=799 else
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'0';
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-- vertical counter
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process(row_en,rst)
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begin
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if(rst='1') then
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row <= (others=>'0');
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elsif(row_en'event and row_en='1') then
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row <= row_next;
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end if;
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end process;
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row_next <= (others=>'0') when row=520 else
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row + 1;
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--output logic
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pixel_x <= std_logic_vector(column);
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pixel_y <= std_logic_vector(row);
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last_column <= '1' when column=639 else
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'0';
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last_row <= '1' when row=479 else
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'0';
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HS <= '0' when column >= 656 and column <= 751 else
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'1';
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VS <= '0' when row >= 490 and row <= 491 else
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'1';
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blank <= '0' when column >= 0 and column <= 639 and row >= 0 and row <= 479 else
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'1';
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end vga_arch; |