78 lines
2.2 KiB
VHDL
78 lines
2.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity seven_segment_display is
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generic(
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COUNTER_BITS: natural := 15
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);
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port(
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clk: in std_logic;
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data_in: in std_logic_vector(15 downto 0);
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dp_in: in std_logic_vector(3 downto 0);
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blank: in std_logic_vector(3 downto 0);
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seg: out std_logic_vector(6 downto 0);
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dp: out std_logic;
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an: out std_logic_vector(3 downto 0)
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);
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end seven_segment_display;
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architecture seven_arch of seven_segment_display is
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--signal which_sym: std_logic_vector(3 downto 0);
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signal mydatain, an_temp: std_logic_vector(3 downto 0);
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signal r_reg: unsigned(COUNTER_BITS-1 downto 0):=(others=>'0');
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signal r_next: unsigned(COUNTER_BITS-1 downto 0);
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signal anode_select: std_logic_vector(1 downto 0);
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begin
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--register
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process(clk)
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begin
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if clk'event and clk='1' then
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r_reg <= r_next;
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end if;
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end process;
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--next-state logic
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process(r_reg)
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begin
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r_next <= r_reg+1;
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end process;
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anode_select <= std_logic_vector(r_reg(COUNTER_BITS-1 downto COUNTER_BITS-2));
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with mydatain select
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seg <= "1000000" when "0000",
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"1111001" when "0001",
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"0100100" when "0010",
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"0110000" when "0011",
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"0011001" when "0100",
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"0010010" when "0101",
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"0000010" when "0110",
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"1111000" when "0111",
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"0000000" when "1000",
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"0010000" when "1001",
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"0001000" when "1010",
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"0000011" when "1011",
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"1000110" when "1100",
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"0100001" when "1101",
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"0000110" when "1110",
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"0001110" when others;
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mydatain <= data_in(3 downto 0) when anode_select = "00" else
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data_in(7 downto 4) when anode_select = "01" else
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data_in(11 downto 8) when anode_select = "10" else
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data_in(15 downto 12);
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dp <= not dp_in(0) when anode_select="00" else
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not dp_in(1) when anode_select="01" else
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not dp_in(2) when anode_select="10" else
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not dp_in(3);
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an_temp <= "1110" when anode_select="00" else
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"1101" when anode_select="01" else
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"1011" when anode_select="10" else
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"0111" when anode_select="11" else
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"0000";
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an <= an_temp or blank;
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end seven_arch; |