76 lines
2.0 KiB
VHDL
76 lines
2.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity charGen is
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port(
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clk: in std_logic;
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char_we: in std_logic;
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char_value: in std_logic_vector(7 downto 0);
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char_addr: in std_logic_vector(11 downto 0);
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pixel_x, pixel_y: in std_logic_vector(9 downto 0);
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pixel_out: out std_logic
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);
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end charGen;
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architecture charGen_arch of charGen is
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component char_mem
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port(
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clk: in std_logic;
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char_read_addr : in std_logic_vector(11 downto 0);
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char_write_addr: in std_logic_vector(11 downto 0);
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char_we : in std_logic;
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char_write_value : in std_logic_vector(7 downto 0);
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char_read_value : out std_logic_vector(7 downto 0)
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);
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end component;
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component font_rom
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port(
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clk: in std_logic;
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addr: in std_logic_vector(10 downto 0);
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data: out std_logic_vector(7 downto 0)
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);
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end component;
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signal rom_addr: std_logic_vector(10 downto 0);
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signal ram_read_addr: std_logic_vector(11 downto 0);
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signal ram_value: std_logic_vector(7 downto 0);
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signal myselect: std_logic_vector(2 downto 0);
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signal tempvar: std_logic_vector(2 downto 0);
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signal rom_data_out: std_logic_vector(7 downto 0);
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begin
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myRam: char_mem
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port map(clk=>clk, char_read_addr=>ram_read_addr, char_write_addr=>char_addr, char_we=>char_we, char_write_value=>char_value, char_read_value=>ram_value
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);
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myRom: font_rom
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port map(clk=>clk, addr=>rom_addr, data=>rom_data_out
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);
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process(clk)
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begin
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if(rising_edge(clk)) then
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tempvar <= pixel_x(2 downto 0);
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myselect <= tempvar;
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end if;
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end process;
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with myselect select
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pixel_out <= rom_data_out(7) when "000",
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rom_data_out(6) when "001",
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rom_data_out(5) when "010",
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rom_data_out(4) when "011",
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rom_data_out(3) when "100",
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rom_data_out(2) when "101",
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rom_data_out(1) when "110",
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rom_data_out(0) when others;
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ram_read_addr <= pixel_y(8 downto 4) & pixel_x(9 downto 3);
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rom_addr <= ram_value(6 downto 0) & pixel_y(3 downto 0);
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end charGen_arch; |