179 lines
3.8 KiB
VHDL
179 lines
3.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity rx is
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generic(
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CLK_RATE: natural := 50_000_000;
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BAUD_RATE: natural := 19_200
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);
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port(
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clk: in std_logic;
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rst: in std_logic;
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rx_in: in std_logic;
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data_out: out std_logic_vector(7 downto 0);
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data_strobe: out std_logic;
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rx_busy:out std_logic
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--send_character: in std_logic;
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);
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end rx;
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architecture receive_arch of rx is
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function log2c(n: integer) return integer is
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variable m, p: integer;
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begin
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m := 0;
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p := 1;
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while p<n loop
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m:= m+1;
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p:=p*2;
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end loop;
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return m;
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end log2c;
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constant BIT_COUNTER_MAX_VAL : Natural := CLK_RATE / BAUD_RATE - 1;
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constant BIT_COUNTER_BITS : Natural := log2c(BIT_COUNTER_MAX_VAL);
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signal counter: unsigned(BIT_COUNTER_BITS downto 0) := (others=>'0');
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signal counter_next: unsigned(BIT_COUNTER_BITS downto 0);
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type fsm_state_type is
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(power_up,idle,strt,b0,b1,b2,b3,b4,b5,b6,b7,stp);
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signal state_reg, state_next: fsm_state_type;
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-- BitTimer signal
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signal rx_bit: std_logic := '0' ;
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signal rx_bit_half: std_logic := '0' ;
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begin
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-- FSM
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process(clk,rst)
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begin
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if(rst='1') then
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state_reg <= idle;
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elsif(clk'event and clk='1') then
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state_reg <= state_next;
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end if;
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end process;
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process(state_reg,rx_in,rx_bit,rx_bit_half)
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begin
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state_next <= state_reg;
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rx_busy <= '1';
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data_strobe <= '0';
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case state_reg is
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when idle =>
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rx_busy <= '0';
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if(rx_in='0') then
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state_next <= strt;
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end if;
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when strt =>
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if(rx_bit='1') then
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state_next <= b0;
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end if;
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when b0 =>
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if(rx_bit='1') then
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state_next <= b1;
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else
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if(rx_bit_half='1') then
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data_out(0) <= rx_in;
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end if;
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end if;
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when b1 =>
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if(rx_bit='1') then
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state_next <= b2;
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else
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if(rx_bit_half='1') then
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data_out(1) <= rx_in;
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end if;
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end if;
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when b2 =>
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if(rx_bit='1') then
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state_next <= b3;
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else
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if(rx_bit_half='1') then
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data_out(2) <= rx_in;
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end if;
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end if;
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when b3 =>
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if(rx_bit='1') then
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state_next <= b4;
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else
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if(rx_bit_half='1') then
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data_out(3) <= rx_in;
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end if;
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end if;
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when b4 =>
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if(rx_bit='1') then
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state_next <= b5;
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else
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if(rx_bit_half='1') then
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data_out(4) <= rx_in;
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end if;
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end if;
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when b5 =>
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if(rx_bit='1') then
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state_next <= b6;
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else
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if(rx_bit_half='1') then
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data_out(5) <= rx_in;
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end if;
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end if;
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when b6 =>
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if(rx_bit='1') then
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state_next <= b7;
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else
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if(rx_bit_half='1') then
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data_out(6) <= rx_in;
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end if;
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end if;
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when b7 =>
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if(rx_bit='1') then
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state_next <= stp;
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else
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if(rx_bit_half='1') then
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data_out(7) <= rx_in;
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end if;
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end if;
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when stp =>
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if(rx_bit='0') then
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state_next <= stp;
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elsif(rx_bit='1' and rx_in='1') then
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state_next <= idle;
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data_strobe <= '1';
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elsif (rx_bit='1' and rx_in='0') then
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state_next <= power_up;
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end if;
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when power_up =>
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if(rx_in='1') then
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state_next <= idle;
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end if;
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end case;
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end process;
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--data_strobe <= '1' when (state_reg=stp) and (state_next=idle) else
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-- '0';
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-- BitTimer
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process(clk,rst)
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begin
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if(rst='1') then
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counter <= (others=>'0');
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elsif(clk'event and clk='1') then
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counter <= counter_next;
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end if;
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end process;
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counter_next <= (others=>'0') when counter = to_unsigned(BIT_COUNTER_MAX_VAL,BIT_COUNTER_BITS) else
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(others=>'0') when state_reg = idle else
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counter+1;
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rx_bit <= '1' when counter = to_unsigned(BIT_COUNTER_MAX_VAL,BIT_COUNTER_BITS) else
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'0';
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rx_bit_half <= '1' when counter= to_unsigned(BIT_COUNTER_MAX_VAL, BIT_COUNTER_BITS)/2 else
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'0';
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end receive_arch; |