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291 lines
13 KiB
291 lines
13 KiB
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#ifndef XAC97_L_H_
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#define XAC97_L_H_
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#ifndef XAC97_H
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#define XAC97_H
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#include <xbasic_types.h>
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#include <xio.h>
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// AC97 core register offsets
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#define AC97_IN_FIFO_OFFSET 0x0
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#define AC97_OUT_FIFO_OFFSET 0x0
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#define AC97_STATUS_OFFSET 0x4
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#define AC97_CONTROL_OFFSET 0x4
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#define AC97_REG_READ_OFFSET 0x8
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#define AC97_REG_WRITE_OFFSET 0x8
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#define AC97_REG_CONTROL_OFFSET 0xc
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// Status register bitmask constants
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#define AC97_IN_FIFO_FULL 0x01
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#define AC97_IN_FIFO_EMPTY 0x02
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#define AC97_OUT_FIFO_EMPTY 0x04
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#define AC97_OUT_FIFO_DATA 0x08
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//#define AC97_REG_ACCESS_FINISHED 0x10
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#define AC97_REG_ACCESS_BUSY 0x10
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#define AC97_CODEC_RDY 0x20
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#define AC97_IN_FIFO_UNDERRUN 0x40
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#define AC97_OUT_FIFO_OVERRUN 0x80
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#define AC97_REG_ACCESS_ERROR 0x100
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#define AC97_IN_FIFO_LEVEL 0x003ff000 // 21 downto 12
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#define AC97_IN_FIFO_LEVEL_RSHFT 12
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#define AC97_OUT_FIFO_LEVEL 0xffc00000 // 31 downto 22
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#define AC97_OUT_FIFO_LEVEL_RSHFT 22
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// FIFO Control Offsets
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#define AC97_CLEAR_IN_FIFO 0x1
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#define AC97_CLEAR_OUT_FIFO 0x2
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#define AC97_ENABLE_IN_FIFO_INTERRUPT 0x4
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#define AC97_ENABLE_OUT_FIFO_INTERRUPT 0x8
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#define AC97_ENABLE_RESET_AC97 0x10
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#define AC97_DISABLE_RESET_AC97 0x0
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#define AC97_CLEAR_FIFOS AC97_CLEAR_IN_FIFO | AC97_CLEAR_OUT_FIFO
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/** AC97 CODEC Registers **/
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#define AC97_Reset 0x00
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#define AC97_MasterVol 0x02
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#define AC97_AuxOutVol 0x04
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#define AC97_MasterVolMono 0x06
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#define AC97_Reserved0x08 0x08
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#define AC97_PCBeepVol 0x0A
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#define AC97_PhoneInVol 0x0C
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#define AC97_MicVol 0x0E
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#define AC97_LineInVol 0x10
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#define AC97_CDVol 0x12
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#define AC97_VideoVol 0x14
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#define AC97_AuxInVol 0x16
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#define AC97_PCMOutVol 0x18
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#define AC97_RecordSelect 0x1A
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#define AC97_RecordGain 0x1C
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#define AC97_Reserved0x1E 0x1E
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#define AC97_GeneralPurpose 0x20
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#define AC97_3DControl 0x22
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#define AC97_PowerDown 0x26
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#define AC97_ExtendedAudioID 0x28
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#define AC97_ExtendedAudioStat 0x2A
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#define AC97_PCM_DAC_Rate 0x2C
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#define AC97_PCM_ADC_Rate 0x32
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#define AC97_PCM_DAC_Rate0 0x78
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#define AC97_PCM_DAC_Rate1 0x7A
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#define AC97_Reserved0x34 0x34
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#define AC97_JackSense 0x72
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#define AC97_SerialConfig 0x74
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#define AC97_MiscControlBits 0x76
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#define AC97_VendorID1 0x7C
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#define AC97_VendorID2 0x7E
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// Volume Constants for registers:
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// AC97_MasterVol
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// AC97_HeadphoneVol
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// AC97_MasterVolMono
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#define AC97_RIGHT_VOL_ATTN_0_DB 0x0
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#define AC97_RIGHT_VOL_ATTN_1_5_DB 0x1
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#define AC97_RIGHT_VOL_ATTN_3_0_DB 0x2
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#define AC97_RIGHT_VOL_ATTN_4_5_DB 0x3
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#define AC97_RIGHT_VOL_ATTN_6_0_DB 0x4
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#define AC97_RIGHT_VOL_ATTN_7_5_DB 0x5
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#define AC97_RIGHT_VOL_ATTN_9_0_DB 0x6
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#define AC97_RIGHT_VOL_ATTN_10_0_DB 0x7
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#define AC97_RIGHT_VOL_ATTN_11_5_DB 0x8
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#define AC97_RIGHT_VOL_ATTN_13_0_DB 0x9
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#define AC97_RIGHT_VOL_ATTN_14_5_DB 0xa
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#define AC97_RIGHT_VOL_ATTN_16_0_DB 0xb
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#define AC97_RIGHT_VOL_ATTN_17_5_DB 0xc
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#define AC97_RIGHT_VOL_ATTN_19_0_DB 0xd
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#define AC97_RIGHT_VOL_ATTN_20_5_DB 0xe
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#define AC97_RIGHT_VOL_ATTN_22_0_DB 0xf
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#define AC97_RIGHT_VOL_ATTN_23_5_DB 0x10
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#define AC97_RIGHT_VOL_ATTN_25_0_DB 0x11
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#define AC97_RIGHT_VOL_ATTN_26_5_DB 0x12
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#define AC97_RIGHT_VOL_ATTN_28_0_DB 0x13
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#define AC97_RIGHT_VOL_ATTN_29_5_DB 0x14
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#define AC97_RIGHT_VOL_ATTN_31_0_DB 0x15
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#define AC97_RIGHT_VOL_ATTN_32_5_DB 0x16
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#define AC97_RIGHT_VOL_ATTN_34_0_DB 0x17
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#define AC97_RIGHT_VOL_ATTN_35_5_DB 0x18
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#define AC97_RIGHT_VOL_ATTN_37_0_DB 0x19
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#define AC97_RIGHT_VOL_ATTN_38_5_DB 0x1a
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#define AC97_RIGHT_VOL_ATTN_40_0_DB 0x1b
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#define AC97_RIGHT_VOL_ATTN_41_5_DB 0x1c
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#define AC97_RIGHT_VOL_ATTN_43_0_DB 0x1d
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#define AC97_RIGHT_VOL_ATTN_44_5_DB 0x1e
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#define AC97_RIGHT_VOL_ATTN_46_0_DB 0x1f
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#define AC97_LEFT_VOL_ATTN_0_DB 0x0
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#define AC97_LEFT_VOL_ATTN_1_5_DB 0x100
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#define AC97_LEFT_VOL_ATTN_3_0_DB 0x200
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#define AC97_LEFT_VOL_ATTN_4_5_DB 0x300
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#define AC97_LEFT_VOL_ATTN_6_0_DB 0x400
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#define AC97_LEFT_VOL_ATTN_7_5_DB 0x500
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#define AC97_LEFT_VOL_ATTN_9_0_DB 0x600
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#define AC97_LEFT_VOL_ATTN_10_0_DB 0x700
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#define AC97_LEFT_VOL_ATTN_11_5_DB 0x800
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#define AC97_LEFT_VOL_ATTN_13_0_DB 0x900
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#define AC97_LEFT_VOL_ATTN_14_5_DB 0xa00
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#define AC97_LEFT_VOL_ATTN_16_0_DB 0xb00
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#define AC97_LEFT_VOL_ATTN_17_5_DB 0xc00
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#define AC97_LEFT_VOL_ATTN_19_0_DB 0xd00
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#define AC97_LEFT_VOL_ATTN_20_5_DB 0xe00
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#define AC97_LEFT_VOL_ATTN_22_0_DB 0xf00
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#define AC97_LEFT_VOL_ATTN_23_5_DB 0x1000
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#define AC97_LEFT_VOL_ATTN_25_0_DB 0x1100
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#define AC97_LEFT_VOL_ATTN_26_5_DB 0x1200
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#define AC97_LEFT_VOL_ATTN_28_0_DB 0x1300
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#define AC97_LEFT_VOL_ATTN_29_5_DB 0x1400
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#define AC97_LEFT_VOL_ATTN_31_0_DB 0x1500
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#define AC97_LEFT_VOL_ATTN_32_5_DB 0x1600
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#define AC97_LEFT_VOL_ATTN_34_0_DB 0x1700
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#define AC97_LEFT_VOL_ATTN_35_5_DB 0x1800
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#define AC97_LEFT_VOL_ATTN_37_0_DB 0x1900
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#define AC97_LEFT_VOL_ATTN_38_5_DB 0x1a00
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#define AC97_LEFT_VOL_ATTN_40_0_DB 0x1b00
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#define AC97_LEFT_VOL_ATTN_41_5_DB 0x1c00
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#define AC97_LEFT_VOL_ATTN_43_0_DB 0x1d00
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#define AC97_LEFT_VOL_ATTN_44_5_DB 0x1e00
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#define AC97_LEFT_VOL_ATTN_46_0_DB 0x1f00
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#define AC97_VOL_ATTN_0_DB AC97_LEFT_VOL_ATTN_0_DB | AC97_RIGHT_VOL_ATTN_0_DB
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#define AC97_VOL_ATTN_1_5_DB AC97_LEFT_VOL_ATTN_1_5_DB | AC97_RIGHT_VOL_ATTN_1_5_DB
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#define AC97_VOL_ATTN_3_0_DB AC97_LEFT_VOL_ATTN_3_0_DB | AC97_RIGHT_VOL_ATTN_3_0_DB
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#define AC97_VOL_ATTN_4_5_DB AC97_LEFT_VOL_ATTN_4_5_DB | AC97_RIGHT_VOL_ATTN_4_5_DB
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#define AC97_VOL_ATTN_6_0_DB AC97_LEFT_VOL_ATTN_6_0_DB | AC97_RIGHT_VOL_ATTN_6_0_DB
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#define AC97_VOL_ATTN_7_5_DB AC97_LEFT_VOL_ATTN_7_5_DB | AC97_RIGHT_VOL_ATTN_7_5_DB
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#define AC97_VOL_ATTN_9_0_DB AC97_LEFT_VOL_ATTN_9_0_DB | AC97_RIGHT_VOL_ATTN_9_0_DB
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#define AC97_VOL_ATTN_10_0_DB AC97_LEFT_VOL_ATTN_10_0_DB | AC97_RIGHT_VOL_ATTN_10_0_DB
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#define AC97_VOL_ATTN_11_5_DB AC97_LEFT_VOL_ATTN_11_5_DB | AC97_RIGHT_VOL_ATTN_11_5_DB
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#define AC97_VOL_ATTN_13_0_DB AC97_LEFT_VOL_ATTN_13_0_DB | AC97_RIGHT_VOL_ATTN_13_0_DB
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#define AC97_VOL_ATTN_14_5_DB AC97_LEFT_VOL_ATTN_14_5_DB | AC97_RIGHT_VOL_ATTN_14_5_DB
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#define AC97_VOL_ATTN_16_0_DB AC97_LEFT_VOL_ATTN_16_0_DB | AC97_RIGHT_VOL_ATTN_16_0_DB
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#define AC97_VOL_ATTN_17_5_DB AC97_LEFT_VOL_ATTN_17_5_DB | AC97_RIGHT_VOL_ATTN_17_5_DB
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#define AC97_VOL_ATTN_19_0_DB AC97_LEFT_VOL_ATTN_19_0_DB | AC97_RIGHT_VOL_ATTN_19_0_DB
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#define AC97_VOL_ATTN_20_5_DB AC97_LEFT_VOL_ATTN_20_5_DB | AC97_RIGHT_VOL_ATTN_20_5_DB
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#define AC97_VOL_ATTN_22_0_DB AC97_LEFT_VOL_ATTN_22_0_DB | AC97_RIGHT_VOL_ATTN_22_0_DB
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#define AC97_VOL_ATTN_23_5_DB AC97_LEFT_VOL_ATTN_23_5_DB | AC97_RIGHT_VOL_ATTN_23_5_DB
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#define AC97_VOL_ATTN_25_0_DB AC97_LEFT_VOL_ATTN_25_0_DB | AC97_RIGHT_VOL_ATTN_25_0_DB
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#define AC97_VOL_ATTN_26_5_DB AC97_LEFT_VOL_ATTN_26_5_DB | AC97_RIGHT_VOL_ATTN_26_5_DB
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#define AC97_VOL_ATTN_28_0_DB AC97_LEFT_VOL_ATTN_28_0_DB | AC97_RIGHT_VOL_ATTN_28_0_DB
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#define AC97_VOL_ATTN_29_5_DB AC97_LEFT_VOL_ATTN_29_5_DB | AC97_RIGHT_VOL_ATTN_29_5_DB
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#define AC97_VOL_ATTN_31_0_DB AC97_LEFT_VOL_ATTN_31_0_DB | AC97_RIGHT_VOL_ATTN_31_0_DB
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#define AC97_VOL_ATTN_32_5_DB AC97_LEFT_VOL_ATTN_32_5_DB | AC97_RIGHT_VOL_ATTN_32_5_DB
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#define AC97_VOL_ATTN_34_0_DB AC97_LEFT_VOL_ATTN_34_0_DB | AC97_RIGHT_VOL_ATTN_34_0_DB
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#define AC97_VOL_ATTN_35_5_DB AC97_LEFT_VOL_ATTN_35_5_DB | AC97_RIGHT_VOL_ATTN_35_5_DB
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#define AC97_VOL_ATTN_37_0_DB AC97_LEFT_VOL_ATTN_37_0_DB | AC97_RIGHT_VOL_ATTN_37_0_DB
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#define AC97_VOL_ATTN_38_5_DB AC97_LEFT_VOL_ATTN_38_5_DB | AC97_RIGHT_VOL_ATTN_38_5_DB
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#define AC97_VOL_ATTN_40_0_DB AC97_LEFT_VOL_ATTN_40_0_DB | AC97_RIGHT_VOL_ATTN_40_0_DB
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#define AC97_VOL_ATTN_41_5_DB AC97_LEFT_VOL_ATTN_41_5_DB | AC97_RIGHT_VOL_ATTN_41_5_DB
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#define AC97_VOL_ATTN_43_0_DB AC97_LEFT_VOL_ATTN_43_0_DB | AC97_RIGHT_VOL_ATTN_43_0_DB
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#define AC97_VOL_ATTN_44_5_DB AC97_LEFT_VOL_ATTN_44_5_DB | AC97_RIGHT_VOL_ATTN_44_5_DB
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#define AC97_VOL_ATTN_46_0_DB AC97_LEFT_VOL_ATTN_46_0_DB | AC97_RIGHT_VOL_ATTN_46_0_DB
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#define AC97_VOL_MUTE 0x8000
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#define AC97_VOL_MIN 0x1f1f
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#define AC97_VOL_MID 0x0a0a
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#define AC97_VOL_MAX 0x0000
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#define AC97_RECORD_MIC_IN 0x0000
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#define AC97_RECORD_LINE_IN 0x0404 // both left and right
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// Extended Audio Control
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#define AC97_EXTENDED_AUDIO_CONTROL_VRA 0x1
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// PCM Data rate constants
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// AC97_PCM_DAC_Rate 0x2C
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// AC97_PCM_ADC_Rate 0x32
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#define AC97_PCM_RATE_8000_HZ 0x1F40
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#define AC97_PCM_RATE_11025_HZ 0x2B11
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#define AC97_PCM_RATE_16000_HZ 0x3E80
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#define AC97_PCM_RATE_22050_HZ 0x5622
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#define AC97_PCM_RATE_44100_HZ 0xAC44
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#define AC97_PCM_RATE_48000_HZ 0xBB80
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// General Purpose register constants (LM4549A)
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// bits are zero by default
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#define AC97_GP_PCM_BYPASS_3D 0x8000 // POP bit (on)
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#define AC97_GP_NATIONAL_3D_ON 0x2000 // 3D bit (on)
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#define AC97_GP_MONO_OUTPUT_MIX 0x0 // MIX bit (off)
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#define AC97_GP_MONO_OUTPUT_MIC 0x200 // MIX bit (on)
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#define AC97_GP_MIC_SELECT_MIC1 0x0 // MS bit (off)
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#define AC97_GP_MIC_SELECT_MIC2 0x100 // MS bit (on)
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#define AC97_GP_ADC_DAC_LOOPBACK 0x80 // LPBK bit
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#define AC97_MIC_INPUT 1
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#define AC97_LINE_INPUT 2
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#define AC97_ANALOG_LOOPBACK 1
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#define AC97_DIGITAL_LOOPBACK 2
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#define XAC97_mGetRegister(BaseAddress, offset) \
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XIo_In32((BaseAddress + offset))
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// Macros for reading/writing AC97 core registers
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#define XAC97_mSetInFifoData(BaseAddress, value) \
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XIo_Out32((BaseAddress) + AC97_IN_FIFO_OFFSET,(value))
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#define XAC97_mGetOutFifoData(BaseAddress) \
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XIo_In32((BaseAddress + AC97_OUT_FIFO_OFFSET))
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#define XAC97_mGetStatus(BaseAddress) \
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XIo_In32((BaseAddress + AC97_STATUS_OFFSET))
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#define XAC97_mSetControl(BaseAddress, value) \
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XIo_Out32((BaseAddress) + AC97_CONTROL_OFFSET,(value))
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#define XAC97_mSetAC97RegisterAccessCommand(BaseAddress, value) \
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XIo_Out32((BaseAddress) + AC97_REG_CONTROL_OFFSET,(value))
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#define XAC97_mGetAC97RegisterData(BaseAddress) \
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XIo_In32((BaseAddress + AC97_REG_READ_OFFSET))
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#define XAC97_mSetAC97RegisterData(BaseAddress, value) \
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XIo_Out32((BaseAddress) + AC97_REG_WRITE_OFFSET,(value))
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// Status register macros
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#define XAC97_isInFIFOFull(BaseAddress) \
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(XAC97_mGetStatus(BaseAddress) & AC97_IN_FIFO_FULL)
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#define XAC97_isInFIFOEmpty(BaseAddress) \
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(XAC97_mGetStatus(BaseAddress) & AC97_IN_FIFO_EMPTY)
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#define XAC97_isOutFIFOEmpty(BaseAddress) \
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(XAC97_mGetStatus(BaseAddress) & AC97_OUT_FIFO_EMPTY)
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#define XAC97_isOutFIFOFull(BaseAddress) \
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(XAC97_mGetStatus(BaseAddress) & AC97_OUT_FIFO_FULL)
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#define XAC97_isRegisterAccessFinished(BaseAddress) \
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((XAC97_mGetStatus(BaseAddress) & AC97_REG_ACCESS_BUSY) == 0)
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// (XAC97_mGetStatus(BaseAddress) & AC97_REG_ACCESS_FINISHED))
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#define XAC97_isRegisterAccessError(BaseAddress) \
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((XAC97_mGetStatus(BaseAddress) & AC97_REG_ACCESS_ERROR) > 0)
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#define XAC97_isCodecReady(BaseAddress) \
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(XAC97_mGetStatus(BaseAddress) & AC97_CODEC_RDY)
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#define XAC97_isInFIFOUnderrun(BaseAddress) \
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(XAC97_mGetStatus(BaseAddress) & AC97_IN_FIFO_UNDERRUN)
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#define XAC97_isOutFIFOOverrun(BaseAddress) \
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(XAC97_mGetStatus(BaseAddress) & AC97_OUT_FIFO_UNDERRUN)
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#define XAC97_getInFIFOLevel(BaseAddress) \
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((XAC97_mGetStatus(BaseAddress) & AC97_IN_FIFO_LEVEL) >> \
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AC97_IN_FIFO_LEVEL_RSHFT)
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#define XAC97_getOutFIFOLevel(BaseAddress) \
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((XAC97_mGetStatus(BaseAddress) & AC97_OUT_FIFO_LEVEL) >> \
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AC97_OUT_FIFO_LEVEL_RSHFT)
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// AC97 driver functions
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void XAC97_WriteReg(Xuint32 BaseAddress, Xuint32 RegAddress, Xuint32 Value);
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Xuint32 XAC97_ReadReg(Xuint32 BaseAddress, Xuint32 RegAddress);
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void XAC97_AwaitCodecReady(Xuint32 BaseAddress);
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void XAC97_Delay(Xuint32 Value);
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void XAC97_SoftReset(Xuint32 BaseAddress);
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void XAC97_HardReset(Xuint32 BaseAddress);
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void XAC97_InitAudio(Xuint32 BaseAddress, Xuint8 Loopback);
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void XAC97_EnableInput(Xuint32 BaseAddress, Xuint8 InputType);
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void XAC97_DisableInput(Xuint32 BaseAddress, Xuint8 InputType);
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void XAC97_RecAudio(Xuint32 BaseAddress, Xuint32 StartAddress,
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Xuint32 EndAddress);
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void XAC97_PlayAudio(Xuint32 BaseAddress, Xuint32 StartAddress,
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Xuint32 EndAddress);
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void XAC97_WriteFifo(Xuint32 BaseAddress, Xuint32 Sample);
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Xuint32 XAC97_ReadFifo(Xuint32 BaseAddress);
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void XAC97_ClearFifos(Xuint32 BaseAddress);
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#endif
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#endif
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