Contains the source code from the course work throughout my undergraduate Computer Engineering degree at Brigham Young University. There is a mixture of Go, Python, C, C++, Java, VHDL, Verilog, Matlab, Bash, Assembly, etc..
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xac97_l.h 13KB

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  1. #ifndef XAC97_L_H_
  2. #define XAC97_L_H_
  3. #ifndef XAC97_H
  4. #define XAC97_H
  5. #include <xbasic_types.h>
  6. #include <xio.h>
  7. // AC97 core register offsets
  8. #define AC97_IN_FIFO_OFFSET 0x0
  9. #define AC97_OUT_FIFO_OFFSET 0x0
  10. #define AC97_STATUS_OFFSET 0x4
  11. #define AC97_CONTROL_OFFSET 0x4
  12. #define AC97_REG_READ_OFFSET 0x8
  13. #define AC97_REG_WRITE_OFFSET 0x8
  14. #define AC97_REG_CONTROL_OFFSET 0xc
  15. // Status register bitmask constants
  16. #define AC97_IN_FIFO_FULL 0x01
  17. #define AC97_IN_FIFO_EMPTY 0x02
  18. #define AC97_OUT_FIFO_EMPTY 0x04
  19. #define AC97_OUT_FIFO_DATA 0x08
  20. //#define AC97_REG_ACCESS_FINISHED 0x10
  21. #define AC97_REG_ACCESS_BUSY 0x10
  22. #define AC97_CODEC_RDY 0x20
  23. #define AC97_IN_FIFO_UNDERRUN 0x40
  24. #define AC97_OUT_FIFO_OVERRUN 0x80
  25. #define AC97_REG_ACCESS_ERROR 0x100
  26. #define AC97_IN_FIFO_LEVEL 0x003ff000 // 21 downto 12
  27. #define AC97_IN_FIFO_LEVEL_RSHFT 12
  28. #define AC97_OUT_FIFO_LEVEL 0xffc00000 // 31 downto 22
  29. #define AC97_OUT_FIFO_LEVEL_RSHFT 22
  30. // FIFO Control Offsets
  31. #define AC97_CLEAR_IN_FIFO 0x1
  32. #define AC97_CLEAR_OUT_FIFO 0x2
  33. #define AC97_ENABLE_IN_FIFO_INTERRUPT 0x4
  34. #define AC97_ENABLE_OUT_FIFO_INTERRUPT 0x8
  35. #define AC97_ENABLE_RESET_AC97 0x10
  36. #define AC97_DISABLE_RESET_AC97 0x0
  37. #define AC97_CLEAR_FIFOS AC97_CLEAR_IN_FIFO | AC97_CLEAR_OUT_FIFO
  38. /** AC97 CODEC Registers **/
  39. #define AC97_Reset 0x00
  40. #define AC97_MasterVol 0x02
  41. #define AC97_AuxOutVol 0x04
  42. #define AC97_MasterVolMono 0x06
  43. #define AC97_Reserved0x08 0x08
  44. #define AC97_PCBeepVol 0x0A
  45. #define AC97_PhoneInVol 0x0C
  46. #define AC97_MicVol 0x0E
  47. #define AC97_LineInVol 0x10
  48. #define AC97_CDVol 0x12
  49. #define AC97_VideoVol 0x14
  50. #define AC97_AuxInVol 0x16
  51. #define AC97_PCMOutVol 0x18
  52. #define AC97_RecordSelect 0x1A
  53. #define AC97_RecordGain 0x1C
  54. #define AC97_Reserved0x1E 0x1E
  55. #define AC97_GeneralPurpose 0x20
  56. #define AC97_3DControl 0x22
  57. #define AC97_PowerDown 0x26
  58. #define AC97_ExtendedAudioID 0x28
  59. #define AC97_ExtendedAudioStat 0x2A
  60. #define AC97_PCM_DAC_Rate 0x2C
  61. #define AC97_PCM_ADC_Rate 0x32
  62. #define AC97_PCM_DAC_Rate0 0x78
  63. #define AC97_PCM_DAC_Rate1 0x7A
  64. #define AC97_Reserved0x34 0x34
  65. #define AC97_JackSense 0x72
  66. #define AC97_SerialConfig 0x74
  67. #define AC97_MiscControlBits 0x76
  68. #define AC97_VendorID1 0x7C
  69. #define AC97_VendorID2 0x7E
  70. // Volume Constants for registers:
  71. // AC97_MasterVol
  72. // AC97_HeadphoneVol
  73. // AC97_MasterVolMono
  74. #define AC97_RIGHT_VOL_ATTN_0_DB 0x0
  75. #define AC97_RIGHT_VOL_ATTN_1_5_DB 0x1
  76. #define AC97_RIGHT_VOL_ATTN_3_0_DB 0x2
  77. #define AC97_RIGHT_VOL_ATTN_4_5_DB 0x3
  78. #define AC97_RIGHT_VOL_ATTN_6_0_DB 0x4
  79. #define AC97_RIGHT_VOL_ATTN_7_5_DB 0x5
  80. #define AC97_RIGHT_VOL_ATTN_9_0_DB 0x6
  81. #define AC97_RIGHT_VOL_ATTN_10_0_DB 0x7
  82. #define AC97_RIGHT_VOL_ATTN_11_5_DB 0x8
  83. #define AC97_RIGHT_VOL_ATTN_13_0_DB 0x9
  84. #define AC97_RIGHT_VOL_ATTN_14_5_DB 0xa
  85. #define AC97_RIGHT_VOL_ATTN_16_0_DB 0xb
  86. #define AC97_RIGHT_VOL_ATTN_17_5_DB 0xc
  87. #define AC97_RIGHT_VOL_ATTN_19_0_DB 0xd
  88. #define AC97_RIGHT_VOL_ATTN_20_5_DB 0xe
  89. #define AC97_RIGHT_VOL_ATTN_22_0_DB 0xf
  90. #define AC97_RIGHT_VOL_ATTN_23_5_DB 0x10
  91. #define AC97_RIGHT_VOL_ATTN_25_0_DB 0x11
  92. #define AC97_RIGHT_VOL_ATTN_26_5_DB 0x12
  93. #define AC97_RIGHT_VOL_ATTN_28_0_DB 0x13
  94. #define AC97_RIGHT_VOL_ATTN_29_5_DB 0x14
  95. #define AC97_RIGHT_VOL_ATTN_31_0_DB 0x15
  96. #define AC97_RIGHT_VOL_ATTN_32_5_DB 0x16
  97. #define AC97_RIGHT_VOL_ATTN_34_0_DB 0x17
  98. #define AC97_RIGHT_VOL_ATTN_35_5_DB 0x18
  99. #define AC97_RIGHT_VOL_ATTN_37_0_DB 0x19
  100. #define AC97_RIGHT_VOL_ATTN_38_5_DB 0x1a
  101. #define AC97_RIGHT_VOL_ATTN_40_0_DB 0x1b
  102. #define AC97_RIGHT_VOL_ATTN_41_5_DB 0x1c
  103. #define AC97_RIGHT_VOL_ATTN_43_0_DB 0x1d
  104. #define AC97_RIGHT_VOL_ATTN_44_5_DB 0x1e
  105. #define AC97_RIGHT_VOL_ATTN_46_0_DB 0x1f
  106. #define AC97_LEFT_VOL_ATTN_0_DB 0x0
  107. #define AC97_LEFT_VOL_ATTN_1_5_DB 0x100
  108. #define AC97_LEFT_VOL_ATTN_3_0_DB 0x200
  109. #define AC97_LEFT_VOL_ATTN_4_5_DB 0x300
  110. #define AC97_LEFT_VOL_ATTN_6_0_DB 0x400
  111. #define AC97_LEFT_VOL_ATTN_7_5_DB 0x500
  112. #define AC97_LEFT_VOL_ATTN_9_0_DB 0x600
  113. #define AC97_LEFT_VOL_ATTN_10_0_DB 0x700
  114. #define AC97_LEFT_VOL_ATTN_11_5_DB 0x800
  115. #define AC97_LEFT_VOL_ATTN_13_0_DB 0x900
  116. #define AC97_LEFT_VOL_ATTN_14_5_DB 0xa00
  117. #define AC97_LEFT_VOL_ATTN_16_0_DB 0xb00
  118. #define AC97_LEFT_VOL_ATTN_17_5_DB 0xc00
  119. #define AC97_LEFT_VOL_ATTN_19_0_DB 0xd00
  120. #define AC97_LEFT_VOL_ATTN_20_5_DB 0xe00
  121. #define AC97_LEFT_VOL_ATTN_22_0_DB 0xf00
  122. #define AC97_LEFT_VOL_ATTN_23_5_DB 0x1000
  123. #define AC97_LEFT_VOL_ATTN_25_0_DB 0x1100
  124. #define AC97_LEFT_VOL_ATTN_26_5_DB 0x1200
  125. #define AC97_LEFT_VOL_ATTN_28_0_DB 0x1300
  126. #define AC97_LEFT_VOL_ATTN_29_5_DB 0x1400
  127. #define AC97_LEFT_VOL_ATTN_31_0_DB 0x1500
  128. #define AC97_LEFT_VOL_ATTN_32_5_DB 0x1600
  129. #define AC97_LEFT_VOL_ATTN_34_0_DB 0x1700
  130. #define AC97_LEFT_VOL_ATTN_35_5_DB 0x1800
  131. #define AC97_LEFT_VOL_ATTN_37_0_DB 0x1900
  132. #define AC97_LEFT_VOL_ATTN_38_5_DB 0x1a00
  133. #define AC97_LEFT_VOL_ATTN_40_0_DB 0x1b00
  134. #define AC97_LEFT_VOL_ATTN_41_5_DB 0x1c00
  135. #define AC97_LEFT_VOL_ATTN_43_0_DB 0x1d00
  136. #define AC97_LEFT_VOL_ATTN_44_5_DB 0x1e00
  137. #define AC97_LEFT_VOL_ATTN_46_0_DB 0x1f00
  138. #define AC97_VOL_ATTN_0_DB AC97_LEFT_VOL_ATTN_0_DB | AC97_RIGHT_VOL_ATTN_0_DB
  139. #define AC97_VOL_ATTN_1_5_DB AC97_LEFT_VOL_ATTN_1_5_DB | AC97_RIGHT_VOL_ATTN_1_5_DB
  140. #define AC97_VOL_ATTN_3_0_DB AC97_LEFT_VOL_ATTN_3_0_DB | AC97_RIGHT_VOL_ATTN_3_0_DB
  141. #define AC97_VOL_ATTN_4_5_DB AC97_LEFT_VOL_ATTN_4_5_DB | AC97_RIGHT_VOL_ATTN_4_5_DB
  142. #define AC97_VOL_ATTN_6_0_DB AC97_LEFT_VOL_ATTN_6_0_DB | AC97_RIGHT_VOL_ATTN_6_0_DB
  143. #define AC97_VOL_ATTN_7_5_DB AC97_LEFT_VOL_ATTN_7_5_DB | AC97_RIGHT_VOL_ATTN_7_5_DB
  144. #define AC97_VOL_ATTN_9_0_DB AC97_LEFT_VOL_ATTN_9_0_DB | AC97_RIGHT_VOL_ATTN_9_0_DB
  145. #define AC97_VOL_ATTN_10_0_DB AC97_LEFT_VOL_ATTN_10_0_DB | AC97_RIGHT_VOL_ATTN_10_0_DB
  146. #define AC97_VOL_ATTN_11_5_DB AC97_LEFT_VOL_ATTN_11_5_DB | AC97_RIGHT_VOL_ATTN_11_5_DB
  147. #define AC97_VOL_ATTN_13_0_DB AC97_LEFT_VOL_ATTN_13_0_DB | AC97_RIGHT_VOL_ATTN_13_0_DB
  148. #define AC97_VOL_ATTN_14_5_DB AC97_LEFT_VOL_ATTN_14_5_DB | AC97_RIGHT_VOL_ATTN_14_5_DB
  149. #define AC97_VOL_ATTN_16_0_DB AC97_LEFT_VOL_ATTN_16_0_DB | AC97_RIGHT_VOL_ATTN_16_0_DB
  150. #define AC97_VOL_ATTN_17_5_DB AC97_LEFT_VOL_ATTN_17_5_DB | AC97_RIGHT_VOL_ATTN_17_5_DB
  151. #define AC97_VOL_ATTN_19_0_DB AC97_LEFT_VOL_ATTN_19_0_DB | AC97_RIGHT_VOL_ATTN_19_0_DB
  152. #define AC97_VOL_ATTN_20_5_DB AC97_LEFT_VOL_ATTN_20_5_DB | AC97_RIGHT_VOL_ATTN_20_5_DB
  153. #define AC97_VOL_ATTN_22_0_DB AC97_LEFT_VOL_ATTN_22_0_DB | AC97_RIGHT_VOL_ATTN_22_0_DB
  154. #define AC97_VOL_ATTN_23_5_DB AC97_LEFT_VOL_ATTN_23_5_DB | AC97_RIGHT_VOL_ATTN_23_5_DB
  155. #define AC97_VOL_ATTN_25_0_DB AC97_LEFT_VOL_ATTN_25_0_DB | AC97_RIGHT_VOL_ATTN_25_0_DB
  156. #define AC97_VOL_ATTN_26_5_DB AC97_LEFT_VOL_ATTN_26_5_DB | AC97_RIGHT_VOL_ATTN_26_5_DB
  157. #define AC97_VOL_ATTN_28_0_DB AC97_LEFT_VOL_ATTN_28_0_DB | AC97_RIGHT_VOL_ATTN_28_0_DB
  158. #define AC97_VOL_ATTN_29_5_DB AC97_LEFT_VOL_ATTN_29_5_DB | AC97_RIGHT_VOL_ATTN_29_5_DB
  159. #define AC97_VOL_ATTN_31_0_DB AC97_LEFT_VOL_ATTN_31_0_DB | AC97_RIGHT_VOL_ATTN_31_0_DB
  160. #define AC97_VOL_ATTN_32_5_DB AC97_LEFT_VOL_ATTN_32_5_DB | AC97_RIGHT_VOL_ATTN_32_5_DB
  161. #define AC97_VOL_ATTN_34_0_DB AC97_LEFT_VOL_ATTN_34_0_DB | AC97_RIGHT_VOL_ATTN_34_0_DB
  162. #define AC97_VOL_ATTN_35_5_DB AC97_LEFT_VOL_ATTN_35_5_DB | AC97_RIGHT_VOL_ATTN_35_5_DB
  163. #define AC97_VOL_ATTN_37_0_DB AC97_LEFT_VOL_ATTN_37_0_DB | AC97_RIGHT_VOL_ATTN_37_0_DB
  164. #define AC97_VOL_ATTN_38_5_DB AC97_LEFT_VOL_ATTN_38_5_DB | AC97_RIGHT_VOL_ATTN_38_5_DB
  165. #define AC97_VOL_ATTN_40_0_DB AC97_LEFT_VOL_ATTN_40_0_DB | AC97_RIGHT_VOL_ATTN_40_0_DB
  166. #define AC97_VOL_ATTN_41_5_DB AC97_LEFT_VOL_ATTN_41_5_DB | AC97_RIGHT_VOL_ATTN_41_5_DB
  167. #define AC97_VOL_ATTN_43_0_DB AC97_LEFT_VOL_ATTN_43_0_DB | AC97_RIGHT_VOL_ATTN_43_0_DB
  168. #define AC97_VOL_ATTN_44_5_DB AC97_LEFT_VOL_ATTN_44_5_DB | AC97_RIGHT_VOL_ATTN_44_5_DB
  169. #define AC97_VOL_ATTN_46_0_DB AC97_LEFT_VOL_ATTN_46_0_DB | AC97_RIGHT_VOL_ATTN_46_0_DB
  170. #define AC97_VOL_MUTE 0x8000
  171. #define AC97_VOL_MIN 0x1f1f
  172. #define AC97_VOL_MID 0x0a0a
  173. #define AC97_VOL_MAX 0x0000
  174. #define AC97_RECORD_MIC_IN 0x0000
  175. #define AC97_RECORD_LINE_IN 0x0404 // both left and right
  176. // Extended Audio Control
  177. #define AC97_EXTENDED_AUDIO_CONTROL_VRA 0x1
  178. // PCM Data rate constants
  179. // AC97_PCM_DAC_Rate 0x2C
  180. // AC97_PCM_ADC_Rate 0x32
  181. #define AC97_PCM_RATE_8000_HZ 0x1F40
  182. #define AC97_PCM_RATE_11025_HZ 0x2B11
  183. #define AC97_PCM_RATE_16000_HZ 0x3E80
  184. #define AC97_PCM_RATE_22050_HZ 0x5622
  185. #define AC97_PCM_RATE_44100_HZ 0xAC44
  186. #define AC97_PCM_RATE_48000_HZ 0xBB80
  187. // General Purpose register constants (LM4549A)
  188. // bits are zero by default
  189. #define AC97_GP_PCM_BYPASS_3D 0x8000 // POP bit (on)
  190. #define AC97_GP_NATIONAL_3D_ON 0x2000 // 3D bit (on)
  191. #define AC97_GP_MONO_OUTPUT_MIX 0x0 // MIX bit (off)
  192. #define AC97_GP_MONO_OUTPUT_MIC 0x200 // MIX bit (on)
  193. #define AC97_GP_MIC_SELECT_MIC1 0x0 // MS bit (off)
  194. #define AC97_GP_MIC_SELECT_MIC2 0x100 // MS bit (on)
  195. #define AC97_GP_ADC_DAC_LOOPBACK 0x80 // LPBK bit
  196. #define AC97_MIC_INPUT 1
  197. #define AC97_LINE_INPUT 2
  198. #define AC97_ANALOG_LOOPBACK 1
  199. #define AC97_DIGITAL_LOOPBACK 2
  200. #define XAC97_mGetRegister(BaseAddress, offset) \
  201. XIo_In32((BaseAddress + offset))
  202. // Macros for reading/writing AC97 core registers
  203. #define XAC97_mSetInFifoData(BaseAddress, value) \
  204. XIo_Out32((BaseAddress) + AC97_IN_FIFO_OFFSET,(value))
  205. #define XAC97_mGetOutFifoData(BaseAddress) \
  206. XIo_In32((BaseAddress + AC97_OUT_FIFO_OFFSET))
  207. #define XAC97_mGetStatus(BaseAddress) \
  208. XIo_In32((BaseAddress + AC97_STATUS_OFFSET))
  209. #define XAC97_mSetControl(BaseAddress, value) \
  210. XIo_Out32((BaseAddress) + AC97_CONTROL_OFFSET,(value))
  211. #define XAC97_mSetAC97RegisterAccessCommand(BaseAddress, value) \
  212. XIo_Out32((BaseAddress) + AC97_REG_CONTROL_OFFSET,(value))
  213. #define XAC97_mGetAC97RegisterData(BaseAddress) \
  214. XIo_In32((BaseAddress + AC97_REG_READ_OFFSET))
  215. #define XAC97_mSetAC97RegisterData(BaseAddress, value) \
  216. XIo_Out32((BaseAddress) + AC97_REG_WRITE_OFFSET,(value))
  217. // Status register macros
  218. #define XAC97_isInFIFOFull(BaseAddress) \
  219. (XAC97_mGetStatus(BaseAddress) & AC97_IN_FIFO_FULL)
  220. #define XAC97_isInFIFOEmpty(BaseAddress) \
  221. (XAC97_mGetStatus(BaseAddress) & AC97_IN_FIFO_EMPTY)
  222. #define XAC97_isOutFIFOEmpty(BaseAddress) \
  223. (XAC97_mGetStatus(BaseAddress) & AC97_OUT_FIFO_EMPTY)
  224. #define XAC97_isOutFIFOFull(BaseAddress) \
  225. (XAC97_mGetStatus(BaseAddress) & AC97_OUT_FIFO_FULL)
  226. #define XAC97_isRegisterAccessFinished(BaseAddress) \
  227. ((XAC97_mGetStatus(BaseAddress) & AC97_REG_ACCESS_BUSY) == 0)
  228. // (XAC97_mGetStatus(BaseAddress) & AC97_REG_ACCESS_FINISHED))
  229. #define XAC97_isRegisterAccessError(BaseAddress) \
  230. ((XAC97_mGetStatus(BaseAddress) & AC97_REG_ACCESS_ERROR) > 0)
  231. #define XAC97_isCodecReady(BaseAddress) \
  232. (XAC97_mGetStatus(BaseAddress) & AC97_CODEC_RDY)
  233. #define XAC97_isInFIFOUnderrun(BaseAddress) \
  234. (XAC97_mGetStatus(BaseAddress) & AC97_IN_FIFO_UNDERRUN)
  235. #define XAC97_isOutFIFOOverrun(BaseAddress) \
  236. (XAC97_mGetStatus(BaseAddress) & AC97_OUT_FIFO_UNDERRUN)
  237. #define XAC97_getInFIFOLevel(BaseAddress) \
  238. ((XAC97_mGetStatus(BaseAddress) & AC97_IN_FIFO_LEVEL) >> \
  239. AC97_IN_FIFO_LEVEL_RSHFT)
  240. #define XAC97_getOutFIFOLevel(BaseAddress) \
  241. ((XAC97_mGetStatus(BaseAddress) & AC97_OUT_FIFO_LEVEL) >> \
  242. AC97_OUT_FIFO_LEVEL_RSHFT)
  243. // AC97 driver functions
  244. void XAC97_WriteReg(Xuint32 BaseAddress, Xuint32 RegAddress, Xuint32 Value);
  245. Xuint32 XAC97_ReadReg(Xuint32 BaseAddress, Xuint32 RegAddress);
  246. void XAC97_AwaitCodecReady(Xuint32 BaseAddress);
  247. void XAC97_Delay(Xuint32 Value);
  248. void XAC97_SoftReset(Xuint32 BaseAddress);
  249. void XAC97_HardReset(Xuint32 BaseAddress);
  250. void XAC97_InitAudio(Xuint32 BaseAddress, Xuint8 Loopback);
  251. void XAC97_EnableInput(Xuint32 BaseAddress, Xuint8 InputType);
  252. void XAC97_DisableInput(Xuint32 BaseAddress, Xuint8 InputType);
  253. void XAC97_RecAudio(Xuint32 BaseAddress, Xuint32 StartAddress,
  254. Xuint32 EndAddress);
  255. void XAC97_PlayAudio(Xuint32 BaseAddress, Xuint32 StartAddress,
  256. Xuint32 EndAddress);
  257. void XAC97_WriteFifo(Xuint32 BaseAddress, Xuint32 Sample);
  258. Xuint32 XAC97_ReadFifo(Xuint32 BaseAddress);
  259. void XAC97_ClearFifos(Xuint32 BaseAddress);
  260. #endif
  261. #endif