Contains the source code from the course work throughout my undergraduate Computer Engineering degree at Brigham Young University. There is a mixture of Go, Python, C, C++, Java, VHDL, Verilog, Matlab, Bash, Assembly, etc..
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xac97_l.c 5.6KB

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  1. /***********************************************************************
  2. * Records a buffer of sound from either the Line-In or Mic-In ports
  3. * to the AC97 controller and plays it back through the Line-Out port
  4. * using the AC97.
  5. ***********************************************************************/
  6. #include <xbasic_types.h>
  7. #include <xio.h>
  8. #include "xac97_l.h"
  9. void XAC97_WriteReg(Xuint32 baseaddr, Xuint32 reg_addr, Xuint32 value) {
  10. XAC97_mSetAC97RegisterData(baseaddr, value);
  11. XAC97_mSetAC97RegisterAccessCommand(baseaddr, reg_addr);
  12. while (!XAC97_isRegisterAccessFinished(baseaddr));
  13. }
  14. Xuint32 XAC97_ReadReg(Xuint32 baseaddr, Xuint32 reg_addr) {
  15. XAC97_mSetAC97RegisterAccessCommand(baseaddr, reg_addr | 0x80);
  16. while (!XAC97_isRegisterAccessFinished(baseaddr));
  17. return XAC97_mGetAC97RegisterData(baseaddr);
  18. }
  19. void XAC97_AwaitCodecReady(Xuint32 baseaddr) {
  20. while(!XAC97_isCodecReady(baseaddr));
  21. }
  22. void XAC97_Delay(Xuint32 value) {
  23. volatile int i = value;
  24. while(i-- > 0);
  25. }
  26. void XAC97_SoftReset(Xuint32 BaseAddress) {
  27. XAC97_WriteReg(BaseAddress, AC97_Reset, 0x0000);
  28. /** Set default output volumes **/
  29. XAC97_WriteReg(BaseAddress, AC97_MasterVol, AC97_VOL_MID);
  30. XAC97_WriteReg(BaseAddress, AC97_AuxOutVol, AC97_VOL_MAX);
  31. XAC97_WriteReg(BaseAddress, AC97_MasterVolMono, AC97_VOL_MAX);
  32. XAC97_WriteReg(BaseAddress, AC97_PCMOutVol, AC97_VOL_MAX);
  33. /** Clear the fifos **/
  34. XAC97_ClearFifos(BaseAddress);
  35. }
  36. void XAC97_HardReset(Xuint32 BaseAddress) {
  37. XAC97_mSetControl(BaseAddress, AC97_ENABLE_RESET_AC97);
  38. XAC97_Delay(100000);
  39. XAC97_mSetControl(BaseAddress, AC97_DISABLE_RESET_AC97);
  40. XAC97_Delay(100000);
  41. XAC97_SoftReset(BaseAddress);
  42. }
  43. void XAC97_InitAudio(Xuint32 BaseAddress, Xuint8 Loopback) {
  44. Xuint8 i;
  45. /** Reset audio codec **/
  46. XAC97_SoftReset(BaseAddress);
  47. /** Wait until we receive the ready signal **/
  48. XAC97_AwaitCodecReady(BaseAddress);
  49. if( Loopback == AC97_ANALOG_LOOPBACK ) {
  50. XAC97_WriteReg(BaseAddress, AC97_MicVol, AC97_VOL_MAX);
  51. XAC97_WriteReg(BaseAddress, AC97_LineInVol, AC97_VOL_MAX);
  52. }
  53. else if( Loopback == AC97_DIGITAL_LOOPBACK )
  54. XAC97_WriteReg(BaseAddress, AC97_GeneralPurpose, AC97_GP_ADC_DAC_LOOPBACK);
  55. } // end XAC97_InitAudio()
  56. void XAC97_EnableInput(Xuint32 BaseAddress, Xuint8 InputType) {
  57. XAC97_WriteReg(BaseAddress, AC97_RecordGain, AC97_VOL_MAX);
  58. if( InputType == AC97_MIC_INPUT )
  59. XAC97_WriteReg(BaseAddress, AC97_RecordSelect, AC97_RECORD_MIC_IN);
  60. else if( InputType == AC97_LINE_INPUT )
  61. XAC97_WriteReg(BaseAddress, AC97_RecordSelect, AC97_RECORD_LINE_IN);
  62. }
  63. void XAC97_DisableInput(Xuint32 BaseAddress, Xuint8 InputType) {
  64. XAC97_WriteReg(BaseAddress, AC97_RecordGain, AC97_VOL_MUTE);
  65. if( InputType == AC97_MIC_INPUT )
  66. XAC97_WriteReg(BaseAddress, AC97_MicVol, AC97_VOL_MUTE);
  67. else if( InputType == AC97_LINE_INPUT )
  68. XAC97_WriteReg(BaseAddress, AC97_LineInVol, AC97_VOL_MUTE);
  69. }
  70. void XAC97_RecAudio(Xuint32 BaseAddress, Xuint32 StartAddress,
  71. Xuint32 EndAddress) {
  72. Xuint32 i;
  73. Xuint32 sample;
  74. volatile Xuint32 *sound_ptr = (Xuint32*)StartAddress;
  75. /** Enable VRA Mode **/
  76. XAC97_WriteReg(BaseAddress, AC97_ExtendedAudioStat, 1);
  77. /** Clear out the FIFOs **/
  78. XAC97_ClearFifos(BaseAddress);
  79. /** Wait until we receive the ready signal **/
  80. XAC97_AwaitCodecReady(BaseAddress);
  81. /** Volume settings **/
  82. XAC97_WriteReg(BaseAddress, AC97_MasterVol, AC97_VOL_MUTE);
  83. XAC97_WriteReg(BaseAddress, AC97_AuxOutVol, AC97_VOL_MUTE);
  84. XAC97_WriteReg(BaseAddress, AC97_MasterVolMono, AC97_VOL_MUTE);
  85. XAC97_WriteReg(BaseAddress, AC97_PCBeepVol, AC97_VOL_MUTE);
  86. XAC97_WriteReg(BaseAddress, AC97_PCMOutVol, AC97_VOL_MUTE);
  87. XAC97_WriteReg(BaseAddress, AC97_GeneralPurpose, AC97_GP_PCM_BYPASS_3D);
  88. /** Record the incoming audio **/
  89. while( sound_ptr < (Xuint32*)EndAddress ) {
  90. sample = XAC97_ReadFifo(BaseAddress);
  91. *sound_ptr = sample;
  92. sound_ptr++;
  93. }
  94. } // end XAC97_RecAudio()
  95. void XAC97_PlayAudio(Xuint32 BaseAddress, Xuint32 StartAddress,
  96. Xuint32 EndAddress){
  97. Xuint32 i;
  98. Xuint32 sample;
  99. volatile Xuint32 *sound_ptr = (Xuint32*)StartAddress;
  100. /** Wait for the ready signal **/
  101. XAC97_AwaitCodecReady(BaseAddress);
  102. /** Disable VRA Mode **/
  103. XAC97_WriteReg(BaseAddress, AC97_ExtendedAudioStat, 0);
  104. /** Play Volume Settings **/
  105. XAC97_WriteReg(BaseAddress, AC97_MasterVol, AC97_VOL_MAX);
  106. XAC97_WriteReg(BaseAddress, AC97_AuxOutVol, AC97_VOL_MAX);
  107. XAC97_WriteReg(BaseAddress, AC97_MasterVolMono, AC97_VOL_MAX);
  108. XAC97_WriteReg(BaseAddress, AC97_PCBeepVol, AC97_VOL_MAX);
  109. XAC97_WriteReg(BaseAddress, AC97_PCMOutVol, AC97_VOL_MAX);
  110. XAC97_WriteReg(BaseAddress, AC97_LineInVol, AC97_VOL_MAX);
  111. XAC97_WriteReg(BaseAddress, AC97_MicVol, AC97_VOL_MAX);
  112. /** Clear FIFOs **/
  113. XAC97_ClearFifos(BaseAddress);
  114. while( sound_ptr < (Xuint32*)EndAddress ) {
  115. sample = *sound_ptr;
  116. sound_ptr = sound_ptr + 1;
  117. XAC97_WriteFifo(BaseAddress, sample);
  118. }
  119. XAC97_ClearFifos(BaseAddress);
  120. } // end XAC97_PlayAudio()
  121. Xuint32 XAC97_ReadFifo(Xuint32 BaseAddress) {
  122. while(XAC97_isOutFIFOEmpty(BaseAddress));
  123. return XAC97_mGetOutFifoData(BaseAddress);
  124. }
  125. void XAC97_WriteFifo(Xuint32 BaseAddress, Xuint32 sample) {
  126. while(XAC97_isInFIFOFull(BaseAddress));
  127. XAC97_mSetInFifoData(BaseAddress, sample);
  128. }
  129. void XAC97_ClearFifos(Xuint32 BaseAddress) {
  130. Xuint32 i;
  131. XAC97_mSetControl(BaseAddress, AC97_CLEAR_FIFOS);
  132. for( i = 0; i < 512; i++ )
  133. XAC97_mSetInFifoData(BaseAddress, 0);
  134. }