Contains the source code from the course work throughout my undergraduate Computer Engineering degree at Brigham Young University. There is a mixture of Go, Python, C, C++, Java, VHDL, Verilog, Matlab, Bash, Assembly, etc..
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213 lines
4.5 KiB

/*******************************************************************/
/* */
/* This file is automatically generated by linker script generator.*/
/* */
/* Version: Xilinx EDK 13.4 EDK_O.87xd */
/* */
/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
/* */
/* Description : MicroBlaze Linker Script */
/* */
/*******************************************************************/
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x1000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
/* Define Memories in the system */
MEMORY
{
microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl : ORIGIN = 0x00000050, LENGTH = 0x00007FB0
MCB_DDR2_S0_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x08000000
}
/* Specify the default entry point to the program */
ENTRY(_start)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.vectors.reset 0x00000000 : {
*(.vectors.reset)
}
.vectors.sw_exception 0x00000008 : {
*(.vectors.sw_exception)
}
.vectors.interrupt 0x00000010 : {
*(.vectors.interrupt)
}
.vectors.hw_exception 0x00000020 : {
*(.vectors.hw_exception)
}
.text : {
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
} > MCB_DDR2_S0_AXI_BASEADDR
.init : {
KEEP (*(.init))
} > MCB_DDR2_S0_AXI_BASEADDR
.fini : {
KEEP (*(.fini))
} > MCB_DDR2_S0_AXI_BASEADDR
.ctors : {
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > MCB_DDR2_S0_AXI_BASEADDR
.dtors : {
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > MCB_DDR2_S0_AXI_BASEADDR
.rodata : {
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > MCB_DDR2_S0_AXI_BASEADDR
.sdata2 : {
. = ALIGN(8);
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
. = ALIGN(8);
__sdata2_end = .;
} > MCB_DDR2_S0_AXI_BASEADDR
.sbss2 : {
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > MCB_DDR2_S0_AXI_BASEADDR
.data : {
. = ALIGN(4);
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
__data_end = .;
} > MCB_DDR2_S0_AXI_BASEADDR
.got : {
*(.got)
} > MCB_DDR2_S0_AXI_BASEADDR
.got1 : {
*(.got1)
} > MCB_DDR2_S0_AXI_BASEADDR
.got2 : {
*(.got2)
} > MCB_DDR2_S0_AXI_BASEADDR
.eh_frame : {
*(.eh_frame)
} > MCB_DDR2_S0_AXI_BASEADDR
.jcr : {
*(.jcr)
} > MCB_DDR2_S0_AXI_BASEADDR
.gcc_except_table : {
*(.gcc_except_table)
} > MCB_DDR2_S0_AXI_BASEADDR
.sdata : {
. = ALIGN(8);
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > MCB_DDR2_S0_AXI_BASEADDR
.sbss : {
. = ALIGN(4);
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
. = ALIGN(8);
__sbss_end = .;
} > MCB_DDR2_S0_AXI_BASEADDR
.tdata : {
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > MCB_DDR2_S0_AXI_BASEADDR
.tbss : {
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > MCB_DDR2_S0_AXI_BASEADDR
.bss : {
. = ALIGN(4);
__bss_start = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
__bss_end = .;
} > MCB_DDR2_S0_AXI_BASEADDR
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap : {
. = ALIGN(8);
_heap = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
} > microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl
.stack : {
_stack_end = .;
. += _STACK_SIZE;
. = ALIGN(8);
_stack = .;
__stack = _stack;
} > microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl
_end = .;
}