Contains the source code from the course work throughout my undergraduate Computer Engineering degree at Brigham Young University. There is a mixture of Go, Python, C, C++, Java, VHDL, Verilog, Matlab, Bash, Assembly, etc..
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lscript.ld 4.5KB

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  1. /*******************************************************************/
  2. /* */
  3. /* This file is automatically generated by linker script generator.*/
  4. /* */
  5. /* Version: Xilinx EDK 13.4 EDK_O.87xd */
  6. /* */
  7. /* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
  8. /* */
  9. /* Description : MicroBlaze Linker Script */
  10. /* */
  11. /*******************************************************************/
  12. _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x1000;
  13. _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x400;
  14. /* Define Memories in the system */
  15. MEMORY
  16. {
  17. microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl : ORIGIN = 0x00000050, LENGTH = 0x00007FB0
  18. MCB_DDR2_S0_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x08000000
  19. }
  20. /* Specify the default entry point to the program */
  21. ENTRY(_start)
  22. /* Define the sections, and where they are mapped in memory */
  23. SECTIONS
  24. {
  25. .vectors.reset 0x00000000 : {
  26. *(.vectors.reset)
  27. }
  28. .vectors.sw_exception 0x00000008 : {
  29. *(.vectors.sw_exception)
  30. }
  31. .vectors.interrupt 0x00000010 : {
  32. *(.vectors.interrupt)
  33. }
  34. .vectors.hw_exception 0x00000020 : {
  35. *(.vectors.hw_exception)
  36. }
  37. .text : {
  38. *(.text)
  39. *(.text.*)
  40. *(.gnu.linkonce.t.*)
  41. } > MCB_DDR2_S0_AXI_BASEADDR
  42. .init : {
  43. KEEP (*(.init))
  44. } > MCB_DDR2_S0_AXI_BASEADDR
  45. .fini : {
  46. KEEP (*(.fini))
  47. } > MCB_DDR2_S0_AXI_BASEADDR
  48. .ctors : {
  49. __CTOR_LIST__ = .;
  50. ___CTORS_LIST___ = .;
  51. KEEP (*crtbegin.o(.ctors))
  52. KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
  53. KEEP (*(SORT(.ctors.*)))
  54. KEEP (*(.ctors))
  55. __CTOR_END__ = .;
  56. ___CTORS_END___ = .;
  57. } > MCB_DDR2_S0_AXI_BASEADDR
  58. .dtors : {
  59. __DTOR_LIST__ = .;
  60. ___DTORS_LIST___ = .;
  61. KEEP (*crtbegin.o(.dtors))
  62. KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
  63. KEEP (*(SORT(.dtors.*)))
  64. KEEP (*(.dtors))
  65. __DTOR_END__ = .;
  66. ___DTORS_END___ = .;
  67. } > MCB_DDR2_S0_AXI_BASEADDR
  68. .rodata : {
  69. __rodata_start = .;
  70. *(.rodata)
  71. *(.rodata.*)
  72. *(.gnu.linkonce.r.*)
  73. __rodata_end = .;
  74. } > MCB_DDR2_S0_AXI_BASEADDR
  75. .sdata2 : {
  76. . = ALIGN(8);
  77. __sdata2_start = .;
  78. *(.sdata2)
  79. *(.sdata2.*)
  80. *(.gnu.linkonce.s2.*)
  81. . = ALIGN(8);
  82. __sdata2_end = .;
  83. } > MCB_DDR2_S0_AXI_BASEADDR
  84. .sbss2 : {
  85. __sbss2_start = .;
  86. *(.sbss2)
  87. *(.sbss2.*)
  88. *(.gnu.linkonce.sb2.*)
  89. __sbss2_end = .;
  90. } > MCB_DDR2_S0_AXI_BASEADDR
  91. .data : {
  92. . = ALIGN(4);
  93. __data_start = .;
  94. *(.data)
  95. *(.data.*)
  96. *(.gnu.linkonce.d.*)
  97. __data_end = .;
  98. } > MCB_DDR2_S0_AXI_BASEADDR
  99. .got : {
  100. *(.got)
  101. } > MCB_DDR2_S0_AXI_BASEADDR
  102. .got1 : {
  103. *(.got1)
  104. } > MCB_DDR2_S0_AXI_BASEADDR
  105. .got2 : {
  106. *(.got2)
  107. } > MCB_DDR2_S0_AXI_BASEADDR
  108. .eh_frame : {
  109. *(.eh_frame)
  110. } > MCB_DDR2_S0_AXI_BASEADDR
  111. .jcr : {
  112. *(.jcr)
  113. } > MCB_DDR2_S0_AXI_BASEADDR
  114. .gcc_except_table : {
  115. *(.gcc_except_table)
  116. } > MCB_DDR2_S0_AXI_BASEADDR
  117. .sdata : {
  118. . = ALIGN(8);
  119. __sdata_start = .;
  120. *(.sdata)
  121. *(.sdata.*)
  122. *(.gnu.linkonce.s.*)
  123. __sdata_end = .;
  124. } > MCB_DDR2_S0_AXI_BASEADDR
  125. .sbss : {
  126. . = ALIGN(4);
  127. __sbss_start = .;
  128. *(.sbss)
  129. *(.sbss.*)
  130. *(.gnu.linkonce.sb.*)
  131. . = ALIGN(8);
  132. __sbss_end = .;
  133. } > MCB_DDR2_S0_AXI_BASEADDR
  134. .tdata : {
  135. __tdata_start = .;
  136. *(.tdata)
  137. *(.tdata.*)
  138. *(.gnu.linkonce.td.*)
  139. __tdata_end = .;
  140. } > MCB_DDR2_S0_AXI_BASEADDR
  141. .tbss : {
  142. __tbss_start = .;
  143. *(.tbss)
  144. *(.tbss.*)
  145. *(.gnu.linkonce.tb.*)
  146. __tbss_end = .;
  147. } > MCB_DDR2_S0_AXI_BASEADDR
  148. .bss : {
  149. . = ALIGN(4);
  150. __bss_start = .;
  151. *(.bss)
  152. *(.bss.*)
  153. *(.gnu.linkonce.b.*)
  154. *(COMMON)
  155. . = ALIGN(4);
  156. __bss_end = .;
  157. } > MCB_DDR2_S0_AXI_BASEADDR
  158. _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
  159. _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
  160. /* Generate Stack and Heap definitions */
  161. .heap : {
  162. . = ALIGN(8);
  163. _heap = .;
  164. _heap_start = .;
  165. . += _HEAP_SIZE;
  166. _heap_end = .;
  167. } > microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl
  168. .stack : {
  169. _stack_end = .;
  170. . += _STACK_SIZE;
  171. . = ALIGN(8);
  172. _stack = .;
  173. __stack = _stack;
  174. } > microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl
  175. _end = .;
  176. }