adding ecen 320 final project
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity charGen_toplevel is
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port(
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clk: in std_logic;
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rgb: out std_logic_vector(7 downto 0);
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hs_out, vs_out: out std_logic;
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sw: in std_logic_vector(7 downto 0);
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seg : out std_logic_vector(6 downto 0);
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an : out std_logic_vector(3 downto 0) := "1100";
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dp : out std_logic;
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btn: in std_logic_vector(3 downto 0);
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ps2_clk : IN STD_LOGIC; --clock signal from PS2 keyboard
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ps2_data : IN STD_LOGIC;
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btwn: out std_logic
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);
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end charGen_toplevel;
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architecture top_charGen of charGen_toplevel is
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component ps2_keyboard_to_ascii is
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generic(
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clk_freq : INTEGER := 50_000_000; --system clock frequency in Hz
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ps2_debounce_counter_size : INTEGER := 8 --set such that 2^size/clk_freq = 5us (size = 8 for 50MHz)
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);
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port(
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clk : IN STD_LOGIC; --system clock input
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ps2_clk : IN STD_LOGIC; --clock signal from PS2 keyboard
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ps2_data : IN STD_LOGIC; --data signal from PS2 keyboard
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ascii_code : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
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ascii_new : OUT STD_LOGIC
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);
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end component;
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component charGen is
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port(
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clk: in std_logic;
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char_we: in std_logic;
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char_value: in std_logic_vector(7 downto 0);
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char_addr: in std_logic_vector(11 downto 0);
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pixel_x: in std_logic_vector(9 downto 0);
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pixel_y: in std_logic_vector(9 downto 0);
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pixel_out: out std_logic
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);
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end component;
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component vga_timing is
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port(
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clk, rst: in std_logic;
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HS: out std_logic;
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VS: out std_logic;
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pixel_x, pixel_y: out std_logic_vector(9 downto 0);
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last_column, last_row: out std_logic;
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blank: out std_logic
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);
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end component;
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component seven_segment_display is
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generic(
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COUNT: natural := 15
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);
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port(
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clk: in std_logic;
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data_in: in std_logic_vector(15 downto 0);
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dp_in: in std_logic_Vector(3 downto 0);
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blank: in std_logic_vector(3 downto 0);
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seg : out std_logic_vector(6 downto 0);
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dp : out std_logic;
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an : out std_logic_vector(3 downto 0)
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);
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end component;
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component tx is
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generic(
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CLK_RATE: natural := 50_000_000;
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BAUD_RATE: natural := 19_200
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);
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port(
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clk: in std_logic;
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rst: in std_logic;
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data_in: in std_logic_vector(7 downto 0);
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send_character: in std_logic;
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tx_out: out std_logic;
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tx_busy:out std_logic
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);
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end component;
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signal temp_x,temp_y: std_logic_vector(9 downto 0);
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signal hs,vs: std_logic;
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signal temp_hs,temp_vs: std_logic := '0';
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signal reset: std_logic := '0';
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signal dp_in: std_logic_vector(3 downto 0) := "0000";
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signal blank4: std_logic_vector(3 downto 0) := (others=>'0');
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signal data_in: std_logic_vector(15 downto 0) := (others=>'0');
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signal data_in123: std_logic_vector(7 downto 0) := (others=>'0');
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signal pixel_out: std_logic;
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signal count: natural := 0;
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signal count_next: natural;
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signal count_en: std_logic;
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signal count_key: natural := 0;
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signal count_next_key: natural;
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signal count_en_key: std_logic;
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signal count_en_start: std_logic;
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signal char_we: std_logic;
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signal row_position, column_position: natural := 0;
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signal row_next, column_next: natural;
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signal row_en: std_logic;
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signal char_write_addr: std_logic_vector(11 downto 0) := (others=>'0');
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signal blank: std_logic := '0';
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signal font_color: std_logic_vector(7 downto 0) := (others=>'1');
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signal back_color: std_logic_vector(7 downto 0) := (others => '0');
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signal ascii_new_temp : STD_LOGIC; --output flag indicating new ASCII value
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signal ascii_code_temp : STD_LOGIC_VECTOR(6 DOWNTO 0); --ASCII value
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signal ascii_code_buf : Std_logic_vector(7 downto 0);
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signal go : std_logic:='0';
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signal tx_out : std_logic;
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signal tx_busy: std_logic;
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begin
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bottom_tx: tx
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port map(clk=>clk, rst=>reset, send_character=>ascii_new_temp,
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tx_out=>tx_out, tx_busy=>tx_busy, data_in=>data_in123
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);
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bottom_ps2: ps2_keyboard_to_ascii
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port map(clk=>clk,ps2_clk=>ps2_clk,ps2_data=>ps2_data,ascii_new=>ascii_new_temp,ascii_code=>ascii_code_temp
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);
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bottom_level: vga_timing
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port map(clk=>clk, rst=>reset, pixel_x=>temp_x, pixel_y=>temp_y, blank=>blank,
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HS=>hs, VS=>vs, last_column=>open, last_row=>open
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);
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bottom_charGen: charGen
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port map(clk=>clk, char_we=>char_we, char_value=>ascii_code_buf, char_addr=>char_write_addr, pixel_x=>temp_x, pixel_y=>temp_y, pixel_out=>pixel_out
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);
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bottom_segment: seven_segment_display
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generic map(COUNT=>15)
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port map(clk=>clk, an=>an, seg=>seg, dp=>dp, blank=>blank4,
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data_in=>data_in, dp_in=>dp_in
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);
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ascii_code_buf <= "0" & ascii_code_temp;
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data_in <= "000000000" & ascii_code_temp;
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data_in123 <= std_logic_vector(unsigned("0" & ascii_code_temp) + unsigned(sw));
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-- DELAY for char_gen
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process(clk)
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begin
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if(rising_edge(clk)) then
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count <= count_next;
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end if;
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end process;
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count_next <= 0 when count=3000000 else
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count + 1;
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count_en <= '1' when count=3000000 else
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'0';
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-- ROW AND COL LOGIC
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row_next <= row_position+1 when row_position < 30 else
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0;
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column_next <= column_position+1 when column_position < 79 else
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0;
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row_en <= '1' when column_position = 79 else
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'0';
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char_write_addr <= std_logic_vector(to_unsigned(row_position,5)) & std_logic_vector(to_unsigned(column_position,7));
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font_color <= sw;
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back_color <= not sw;
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-- COLOR
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rgb <= std_logic_vector(font_color) when pixel_out='1' else
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std_logic_vector(back_color) when blank = '0' else
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"00000000";
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btwn <= tx_out;
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process(clk)
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begin
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if(rising_edge(clk)) then
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if(ascii_new_temp = '1') then
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go <='1';
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end if;
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if(char_we = '1') then
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go <='0';
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end if;
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end if;
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end process;
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-- BUTTON
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char_we <= '1' when count_en = '1' and go = '1' else '0';
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process(clk,ascii_new_temp,count_en)
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begin
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if(rising_edge(clk)) then
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if (btn(3)='1') then
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reset <= '1';
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column_position <= 0;
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row_position <= 0;
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elsif (go = '1') then
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if(count_en='1') then
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reset <= '0';
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column_position <= column_next;
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if(row_en='1') then
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row_position <= row_next;
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end if;
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end if;
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else
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reset <= '0';
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end if;
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end if;
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end process;
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-- DELAYS
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process(clk,hs,vs)
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begin
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if(rising_edge(clk)) then
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temp_hs <= hs;
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temp_vs <= vs;
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hs_out <= temp_hs;
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vs_out <= temp_vs;
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end if;
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end process;
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end top_charGen;
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