adding ecen 320 final project
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity charGen_top is
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port(
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clk: in std_logic;
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rgb: out std_logic_vector(7 downto 0);
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hs_out, vs_out: out std_logic;
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sw: in std_logic_vector(7 downto 0);
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seg : out std_logic_vector(6 downto 0);
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an : out std_logic_vector(3 downto 0) := "1100";
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dp : out std_logic;
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rx_in : in std_logic;
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btn: in std_logic_vector(3 downto 0)
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);
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end charGen_top;
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architecture top_charGen of charGen_top is
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component charGen
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port(
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clk: in std_logic;
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char_we: in std_logic;
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char_value: in std_logic_vector(7 downto 0);
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char_addr: in std_logic_vector(11 downto 0);
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pixel_x, pixel_y: in std_logic_vector(9 downto 0);
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pixel_out: out std_logic
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);
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end component;
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component vga_timing is
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port(
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clk, rst: in std_logic;
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HS, VS: out std_logic;
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pixel_x, pixel_y: out std_logic_vector(9 downto 0);
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last_column, last_row: out std_logic;
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blank: out std_logic
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);
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end component;
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component seven_segment_display
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generic(
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COUNTER_BITS: natural := 15
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);
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port(
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clk: in std_logic;
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data_in: in std_logic_vector(15 downto 0);
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dp_in: in std_logic_Vector(3 downto 0);
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blank: in std_logic_vector(3 downto 0);
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seg : out std_logic_vector(6 downto 0);
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dp : out std_logic;
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an : out std_logic_vector(3 downto 0)
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);
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end component;
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component rx
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port(
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clk: in std_logic;
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rst: in std_logic;
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data_out: out std_logic_vector(7 downto 0);
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data_strobe: out std_logic;
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rx_in: in std_logic;
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rx_busy:out std_logic
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);
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end component;
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signal temp_x,temp_y: std_logic_vector(9 downto 0);
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signal hs,vs: std_logic;
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signal temp_hs,temp_vs: std_logic := '0';
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signal reset: std_logic := '0';
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signal dp_in: std_logic_vector(3 downto 0) := "0000";
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signal blank4: std_logic_vector(3 downto 0) := (others=>'0');
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signal data_in: std_logic_vector(15 downto 0) := (others=>'0');
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signal pixel_out: std_logic;
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signal count: natural := 0;
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signal count_next: natural;
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signal count_en: std_logic;
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signal char_we: std_logic;
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signal row_position, column_position: natural := 0;
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signal row_next, column_next: natural;
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signal row_en: std_logic;
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signal char_write_addr: std_logic_vector(11 downto 0) := (others=>'0');
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signal blank: std_logic := '0';
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signal font_color: std_logic_vector(7 downto 0) := (others=>'0');
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signal back_color: std_logic_vector(7 downto 0) := (others=>'0');
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-------rx top signals
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signal reset1: std_logic := '0';
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signal data_out2: std_logic_vector(7 downto 0) := (others=>'0');
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signal data_strobe: std_logic;
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signal reg_left,reg_right: std_logic_vector(7 downto 0) := (others=>'0');
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signal reg_right_temp: std_logic_vector(7 downto 0);
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signal delay_data1, delay_data2: std_logic;
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signal temp: std_logic_vector(15 downto 0) := (others=>'0');
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signal decrypt: std_logic_vector(15 downto 0) := (others=>'0');
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signal go: std_logic := '0';
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begin
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bottom_level: vga_timing
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port map(clk=>clk, rst=>reset, pixel_x=>temp_x, pixel_y=>temp_y, blank=>blank,
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HS=>hs, VS=>vs, last_column=>open, last_row=>open
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);
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bottom_charGen: charGen
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port map(clk=>clk, char_we=>char_we, char_value=>reg_right, char_addr=>char_write_addr, pixel_x=>temp_x, pixel_y=>temp_y, pixel_out=>pixel_out
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);
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-- bottom_segment: seven_segment_display
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-- generic map(COUNTER_BITS=>15)
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-- port map(clk=>clk, an=>an, seg=>seg, dp=>dp, blank=>blank4,
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-- data_in=>data_in, dp_in=>dp_in
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-- );
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--- this is from rx_Top-----
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bottom_segment: seven_segment_display
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generic map(COUNTER_BITS=>15)
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port map(clk=>clk, an=>an, seg=>seg, dp=>dp, blank=>blank4,
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data_in=>temp, dp_in=>dp_in
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);
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bottom_rx: rx
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port map(clk=>clk, rst=>reset1, data_out=>data_out2,
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data_strobe=>data_strobe, rx_in=>delay_data2, rx_busy=>open
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);
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------------rx top code-------------------------
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--temp <= (reg_left & reg_right);
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process(clk)
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begin
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if(rising_edge(clk)) then
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delay_data1 <= rx_in;
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delay_data2 <= delay_data1;
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if(data_strobe='1') then
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reg_left <= reg_right;
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reg_right <= std_logic_vector(unsigned(data_out2) - unsigned(sw));
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end if;
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end if;
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end process;
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------------end of rx top code-----------------
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---------------***********************************-----------------------------
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-- to do decryption you need to make temp signal and take reg_right
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-- and do the subtraction and pipe that temp signal into char_gen line 104
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---------------***********************************-----------------------------
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--reg_right_temp <= reg_right;
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decrypt <= std_logic_vector(std_logic_vector(unsigned(reg_left) - unsigned(sw)) & std_logic_vector(unsigned(reg_right) - unsigned(sw)));
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temp <= decrypt;
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--data_in <= "00000000" & temp;
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data_in <= temp;
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-- delaying counter
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process(clk)
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begin
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if(rising_edge(clk)) then
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count <= count_next;
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end if;
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end process;
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count_next <= 0 when count=4000000 else
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count + 1;
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count_en <= '1' when count=4000000 else
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'0';
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-- row_position, column_position logic
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row_next <= row_position+1 when row_position < 30 else
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0;
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column_next <= column_position+1 when column_position < 79 else
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0;
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row_en <= '1' when column_position = 79 else
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'0';
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char_write_addr <= std_logic_vector(to_unsigned(row_position,5)) & std_logic_vector(to_unsigned(column_position,7));
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font_color <= sw(7 downto 0);
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back_color <= not sw(7 downto 0);
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-- color logic
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rgb <= std_logic_vector(font_color) when pixel_out='1' else
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std_logic_vector(back_color) when blank = '0' else
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"00000000";
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char_we <= '1' when count_en='1' and go = '1' else
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'0';
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process(clk)
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begin
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if(rising_edge(clk)) then
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if(data_strobe = '1') then
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go <='1';
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end if;
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if(char_we = '1') then
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go <='0';
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end if;
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end if;
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end process;
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-- button logic
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process(clk,btn,count_en,go)
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begin
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if(rising_edge(clk)) then
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if (btn(3)='1') then
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reset <= '1';
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column_position <= 0;
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row_position <= 0;
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elsif (go = '1') then
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if(count_en='1') then
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reset <= '0';
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column_position <= column_next;
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if(row_en='1') then
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row_position <= row_next;
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-- font_color <= font_color+1;
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if(row_position=0) then
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--back_color <= back_color+1;
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end if;
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end if;
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end if;
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else
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reset <= '0';
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end if;
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end if;
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end process;
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-- making delays for HS, VS
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process(clk,hs,vs)
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begin
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if(rising_edge(clk)) then
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temp_hs <= hs;
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temp_vs <= vs;
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hs_out <= temp_hs;
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vs_out <= temp_vs;
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end if;
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end process;
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end top_charGen;
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