school/ecen425/clib.s

1112 lines
19 KiB
ArmAsm
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2016-04-10 09:23:15 -07:00
CPU 8086
ORG 0h
InterruptVectorTable:
; Internal x86 Interrupts:
dd 0 ; Reserved (Div err) ; Int 00h
dd 0 ; Reserved (Step) ; Int 01h
dd 0 ; Reserved (NMI) ; Int 02h
dd 0 ; Reserved (Break) ; Int 03h
dd 0 ; Reserved (Overflow) ; Int 04h
dd 0 ; Int 05h
dd 0 ; Int 06h
dd 0 ; Int 07h
; Hardware Interrupts:
dd RESET ; Reset ; Int 08h (IRQ 0)
dd TICK ; Tick ; Int 09h (IRQ 1)
dd KEYBOARD ; Keyboard ; Int 0Ah (IRQ 2)
dd 0 ; Simptris Game Over ; Int 0Bh (IRQ 3)
dd 0 ; Simptris New Piece ; Int 0Ch (IRQ 4)
dd 0 ; Simptris Received ; Int 0Dh (IRQ 5)
dd 0 ; Simptris Touchdown ; Int 0Eh (IRQ 6)
dd 0 ; Simptris Clear ; Int 0Fh (IRQ 7)
; Software Interrupts:
dd 0 ; Reserved (PC BIOS) ; Int 10h
dd 0 ; Int 11h
dd 0 ; Int 12h
dd 0 ; Int 13h
dd 0 ; Int 14h
dd 0 ; Int 15h
dd 0 ; Int 16h
dd 0 ; Int 17h
dd 0 ; Int 18h
dd 0 ; Int 19h
dd 0 ; Int 1Ah
dd 0 ; Int 1Bh
dd 0 ; Int 1Ch
dd 0 ; Int 1Dh
dd 0 ; Int 1Eh
dd 0 ; Int 1Fh
dd TRAP ; Int 20h
dd 0 ; Reserved (DOS) ; Int 21h
dd 0 ; Simptris Services ; Int 22h
dd 0 ; Int 23h
dd 0 ; Int 24h
dd 0 ; Int 25h
dd 0 ; Int 26h
dd 0 ; Int 27h
dd 0 ; Int 28h
dd 0 ; Int 29h
dd 0 ; Int 2Ah
dd 0 ; Int 2Bh
dd 0 ; Int 2Ch
dd 0 ; Int 2Dh
dd 0 ; Int 2Eh
dd 0 ; Int 2Fh
KeyBuffer: ; Address 0xC0
dw 0
NewPieceType: ; Address 0xC2
dw 0
NewPieceID: ; Address 0xC4
dw 0
NewPieceOrientation: ; Address 0xC6
dw 0
NewPieceColumn: ; Address 0xC8
dw 0
TouchdownID: ; Address 0xCA
dw 0
ScreenBitMap0: ; Address 0xCC
dw 0
ScreenBitMap1:
dw 0
ScreenBitMap2:
dw 0
ScreenBitMap3:
dw 0
ScreenBitMap4:
dw 0
ScreenBitMap5:
dw 0
TIMES 100h-($-$$) db 0 ; Fill up to (but not including) address 100h with 0
jmp main
; This file contains support routines for 32-bit on the 8086.
; It is intended for use code generated by the C86 compiler.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
SR_asldiv: ; l1 /= l2
push bp
mov bp,sp
push bx
mov bx,[bp+4] ; Get address of l1 (was push3)
push word [bp+8] ; Push hi l2 (was push1)
push word [bp+6] ; Push lo l2 (was push2)
push word [bx+2] ; Push hi l1
push word [bx] ; Push lo l1
call SR_ldiv
mov bx,[bp+4] ; Restore l1 address
mov [bx+2],dx ; Store result
mov [bx],ax
pop bx
pop bp
ret
SR_aslmod: ; l1 %= l2
push bp
mov bp,sp
push bx
mov bx,[bp+4] ; Get address of l1 (was push3)
push word [bp+8] ; Push hi l2 (was push1)
push word [bp+6] ; Push lo l2 (was push2)
push word [bx+2] ; Push hi l1
push word [bx] ; Push lo l1
call SR_lmod
mov bx,[bp+4] ; Restore l1 address
mov [bx+2],dx ; Store result
mov [bx],ax
pop bx
pop bp
ret
SR_aslmul: ; l1 *= l2
push bp
mov bp,sp
push bx
mov bx,[bp+4] ; Get address of l1 (was push3)
push word [bp+8] ; Push hi l2 (was push1)
push word [bp+6] ; Push lo l2 (was push2)
push word [bx+2] ; Push hi l1
push word [bx] ; Push lo l1
call SR_lmul
add sp,8
mov bx,[bp+4] ; Restore l1 address
mov [bx+2],dx ; Store result
mov [bx],ax
pop bx
pop bp
ret
SR_aslshl: ; l1 <<= l2
push bp
mov bp,sp
push bx
mov bx,[bp+4] ; Get address of l1 (was push3)
push word [bp+8] ; Push hi l2 (was push1)
push word [bp+6] ; Push lo l2 (was push2)
push word [bx+2] ; Push hi l1
push word [bx] ; Push lo l1
call SR_lshl
add sp,8
mov bx,[bp+4] ; Restore l1 address
mov [bx+2],dx ; Store result
mov [bx],ax
pop bx
pop bp
ret
SR_aslshr: ; l1 >>= l2
push bp
mov bp,sp
push bx
mov bx,[bp+4] ; Get address of l1 (was push3)
push word [bp+8] ; Push hi l2 (was push1)
push word [bp+6] ; Push lo l2 (was push2)
push word [bx+2] ; Push hi l1
push word [bx] ; Push lo l1
call SR_lshr
add sp,8
mov bx,[bp+4] ; Restore l1 address
mov [bx+2],dx ; Store result
mov [bx],ax
pop bx
pop bp
ret
SR_asuldiv: ; u1 /= u2
push bp
mov bp,sp
push bx
mov bx,[bp+4] ; Get address of u1 (was push3)
push word [bp+8] ; Push hi u2 (was push1)
push word [bp+6] ; Push lo u2 (was push2)
push word [bx+2] ; Push hi u1
push word [bx] ; Push lo u1
call SR_uldiv
mov bx,[bp+4] ; Restore u1 address
mov [bx+2],dx ; Store result
mov [bx],ax
pop bx
pop bp
ret
SR_asilmod: ; u1 %= u2
push bp
mov bp,sp
push bx
mov bx,[bp+4] ; Get address of u1 (was push3)
push word [bp+8] ; Push hi u2 (was push1)
push word [bp+6] ; Push lo u2 (was push2)
push word [bx+2] ; Push hi u1
push word [bx] ; Push lo u1
call SR_ilmod
mov bx,[bp+4] ; Restore u1 address
mov [bx+2],dx ; Store result
mov [bx],ax
pop bx
pop bp
ret
SR_asulmul: ; u1 *= u2
push bp
mov bp,sp
push bx
mov bx,[bp+4] ; Get address of u1 (was push3)
push word [bp+8] ; Push hi u2 (was push1)
push word [bp+6] ; Push lo u2 (was push2)
push word [bx+2] ; Push hi u1
push word [bx] ; Push lo u1
call SR_ulmul
add sp,8
mov bx,[bp+4] ; Restore u1 address
mov [bx+2],dx ; Store result
mov [bx],ax
pop bx
pop bp
ret
SR_asulshl: ; u1 << u2
push bp
mov bp,sp
push bx
mov bx,[bp+4] ; Get address of u1 (was push3)
push word [bp+8] ; Push hi u2 (was push1)
push word [bp+6] ; Push lo u2 (was push2)
push word [bx+2] ; Push hi u1
push word [bx] ; Push lo u1
call SR_ulshl
add sp,8
mov bx,[bp+4] ; Restore u1 address
mov [bx+2],dx ; Store result
mov [bx],ax
pop bx
pop bp
ret
SR_asulshr: ; u1 >> u2
push bp
mov bp,sp
push bx
mov bx,[bp+4] ; Get address of u1 (was push3)
push word [bp+8] ; Push hi u2 (was push1)
push word [bp+6] ; Push lo u2 (was push2)
push word [bx+2] ; Push hi u1
push word [bx] ; Push lo u1
call SR_ulshr
add sp,8
mov bx,[bp+4] ; Restore u1 address
mov [bx+2],dx ; Store result
mov [bx],ax
pop bx
pop bp
ret
; Main 32-bit routines begin here:
SR_ldiv: ; N_LDIV@
pop cx
push cs
push cx
; LDIV@
xor cx,cx
jmp LSR_01
SR_uldiv: ; N_LUDIV@
pop cx
push cs
push cx
; F_LUDIV@
mov cx,0001
jmp LSR_01
SR_lmod: ; N_LMOD@
pop cx
push cs
push cx
; F_LMOD@
mov cx,0002
jmp LSR_01
SR_ilmod: ; N_LUMOD@
pop cx
push cs
push cx
; LUMOD@
mov cx,0003
LSR_01:
push bp
push si
push di
mov bp,sp
mov di,cx
mov ax,[bp+0Ah]
mov dx,[bp+0Ch]
mov bx,[bp+0Eh]
mov cx,[bp+10h]
or cx,cx
jne LSR_02
or dx,dx
je LSR_10
or bx,bx
je LSR_10
LSR_02:
test di,0001
jne LSR_04
or dx,dx
jns LSR_03
neg dx
neg ax
sbb dx,0000
or di,000Ch
LSR_03:
or cx,cx
jns LSR_04
neg cx
neg bx
sbb cx,0000
xor di,0004
LSR_04:
mov bp,cx
mov cx,0020h
push di
xor di,di
xor si,si
LSR_05:
shl ax,1
rcl dx,1
rcl si,1
rcl di,1
cmp di,bp
jb LSR_07
ja LSR_06
cmp si,bx
jb LSR_07
LSR_06:
sub si,bx
sbb di,bp
inc ax
LSR_07:
loop LSR_05
pop bx
test bx,0002
je LSR_08
mov ax,si
mov dx,di
shr bx,1
LSR_08:
test bx,0004h
je LSR_09
neg dx
neg ax
sbb dx,0000
LSR_09:
pop di
pop si
pop bp
retf 0008
LSR_10:
div bx
test di,0002
je LSR_11
xchg dx,ax
LSR_11:
xor dx,dx
jmp LSR_09
SR_lshl: ; N_LXLSH@
SR_ulshl:
; r = a << b
pop bx
push cs
push bx
push bp
mov bp,sp
push cx ; C86 doesn't expect use of cx or bx
mov ax, [bp+6] ; pop loword(a)
mov dx, [bp+8] ; pop hiword(a)
mov cx, [bp+10] ; pop word(b)
; LXLSH@
cmp cl,10h
jnb LSR_12
mov bx,ax
shl ax,cl
shl dx,cl
neg cl
add cl,10h
shr bx,cl
or dx,bx
pop cx
pop bp
retf
LSR_12:
sub cl,10h
xchg dx,ax
xor ax,ax
shl dx,cl
pop cx
pop bp
retf
SR_lshr: ; N_LXRSH@
; r = a >> b
pop bx
push cs
push bx
push bp
mov bp,sp
push cx ; C86 doesn't expect use of cx or bx
mov ax, [bp+6] ; pop loword(a)
mov dx, [bp+8] ; pop hiword(a)
mov cx, [bp+10] ; pop word(b)
; LXRSH@
cmp cl,10h
jnb LSR_13
mov bx,dx
shr ax,cl
sar dx,cl
neg cl
add cl,10h
shl bx,cl
or ax,bx
pop cx
pop bp
retf
LSR_13:
sub cl,10h
xchg dx,ax
cwd
sar ax,cl
pop cx
pop bp
retf
SR_ulshr: ; N_LXURSH@
; r = a >> b
pop bx
push cs
push bx
push bp
mov bp,sp
push cx ; C86 doesn't expect use of cx or bx
mov ax, [bp+6] ; pop loword(a)
mov dx, [bp+8] ; pop hiword(a)
mov cx, [bp+10] ; pop word(b)
; LXURSH@
cmp cl,10h
jnb LSR_14
mov bx,dx
shr ax,cl
shr dx,cl
neg cl
add cl,10h
shl bx,cl
or ax,bx
pop cx
pop bp
retf
LSR_14:
sub cl,10h
xchg dx,ax
xor dx,dx
shr ax,cl
pop cx
pop bp
retf
SR_lmul: ; N_LXMUL@
SR_ulmul:
; r = a * b
push bp
push si
mov bp,sp
push cx ; C86 doesn't expect use of cx or bx
push bx
mov bx, [bp+6] ; pop loword(a)
mov cx, [bp+8] ; pop hiword(a)
mov ax, [bp+10] ; pop loword(b)
mov dx, [bp+12] ; pop hiword(b)
xchg si,ax
xchg dx,ax
test ax,ax
je LSR_15
mul bx
LSR_15:
jcxz LSR_16
xchg cx,ax
mul si
add ax,cx
LSR_16:
xchg si,ax
mul bx
add dx,si
pop bx
pop cx
pop si
pop bp
ret
; Generated by c86 (BYU-NASM) 5.1 (beta) from clib.c
CPU 8086
ALIGN 2
jmp main ; Jump to program start
new_line:
db 13,10,36
ALIGN 2
signalEOI:
jmp L_clib_1
L_clib_2:
mov al, 0x20
out 0x20, al
mov sp, bp
pop bp
ret
L_clib_1:
push bp
mov bp, sp
jmp L_clib_2
ALIGN 2
exit:
jmp L_clib_4
L_clib_5:
mov ah, 4Ch
mov al, [bp+4]
int 21h
mov sp, bp
pop bp
ret
L_clib_4:
push bp
mov bp, sp
jmp L_clib_5
ALIGN 2
print:
jmp L_clib_7
L_clib_8:
mov ah, 40h
mov bx, 1
mov cx, [bp+6]
mov dx, [bp+4]
int 21h
mov sp, bp
pop bp
ret
L_clib_7:
push bp
mov bp, sp
jmp L_clib_8
ALIGN 2
printChar:
jmp L_clib_10
L_clib_11:
mov ah, 2
mov dl, [bp+4]
int 21h
mov sp, bp
pop bp
ret
L_clib_10:
push bp
mov bp, sp
jmp L_clib_11
ALIGN 2
printNewLine:
jmp L_clib_13
L_clib_14:
mov ah, 9
mov dx, new_line
int 21h
mov sp, bp
pop bp
ret
L_clib_13:
push bp
mov bp, sp
jmp L_clib_14
ALIGN 2
printString:
jmp L_clib_16
L_clib_17:
xor si,si
mov bx, [bp+4]
jmp printString2
printString1:
inc si
printString2:
cmp byte [bx+si],0
jne printString1
mov dx, bx
mov cx, si
mov ah, 40h
mov bx, 1
int 21h
mov sp, bp
pop bp
ret
L_clib_16:
push bp
mov bp, sp
push cx
jmp L_clib_17
ALIGN 2
printInt:
jmp L_clib_19
L_clib_20:
mov word [bp-2], 0
mov word [bp-4], 10000
cmp word [bp+4], 0
jge L_clib_21
mov byte [bp-10], 45
inc word [bp-2]
mov ax, word [bp+4]
neg ax
mov word [bp+4], ax
L_clib_21:
mov ax, word [bp+4]
test ax, ax
jne L_clib_22
mov word [bp-4], 1
jmp L_clib_23
L_clib_22:
jmp L_clib_25
L_clib_24:
mov ax, word [bp-4]
cwd
mov cx, 10
idiv cx
mov word [bp-4], ax
L_clib_25:
mov ax, word [bp+4]
cwd
idiv word [bp-4]
test ax, ax
je L_clib_24
L_clib_26:
L_clib_23:
jmp L_clib_28
L_clib_27:
mov ax, word [bp+4]
xor dx, dx
div word [bp-4]
add al, 48
mov si, word [bp-2]
lea dx, [bp-10]
add si, dx
mov byte [si], al
inc word [bp-2]
mov ax, word [bp+4]
xor dx, dx
div word [bp-4]
mov ax, dx
mov word [bp+4], ax
mov ax, word [bp-4]
cwd
mov cx, 10
idiv cx
mov word [bp-4], ax
mov ax, word [bp-4]
mov word [bp-4], ax
L_clib_28:
cmp word [bp-4], 0
jg L_clib_27
L_clib_29:
push word [bp-2]
lea ax, [bp-10]
push ax
call print
add sp, 4
mov sp, bp
pop bp
ret
L_clib_19:
push bp
mov bp, sp
sub sp, 10
jmp L_clib_20
ALIGN 2
printLong:
jmp L_clib_31
L_clib_32:
mov word [bp-2], 0
mov word [bp-6], 51712
mov word [bp-4], 15258
cmp word [bp+6], 0
jg L_clib_33
jl L_clib_34
cmp word [bp+4], 0
jae L_clib_33
L_clib_34:
mov byte [bp-17], 45
inc word [bp-2]
mov ax, word [bp+4]
mov dx, word [bp+6]
neg ax
adc dx, 0
neg dx
mov word [bp+4], ax
mov word [bp+6], dx
L_clib_33:
mov ax, word [bp+4]
mov dx, word [bp+6]
or dx, ax
jne L_clib_35
mov word [bp-6], 1
mov word [bp-4], 0
jmp L_clib_36
L_clib_35:
jmp L_clib_38
L_clib_37:
mov ax, 10
xor dx, dx
push dx
push ax
lea ax, [bp-6]
push ax
call SR_asldiv
L_clib_38:
push word [bp-4]
push word [bp-6]
push word [bp+6]
push word [bp+4]
call SR_ldiv
or dx, ax
je L_clib_37
L_clib_39:
L_clib_36:
jmp L_clib_41
L_clib_40:
push word [bp-4]
push word [bp-6]
push word [bp+6]
push word [bp+4]
call SR_uldiv
add al, 48
mov si, word [bp-2]
lea dx, [bp-17]
add si, dx
mov byte [si], al
inc word [bp-2]
push word [bp-4]
push word [bp-6]
push word [bp+6]
push word [bp+4]
call SR_lmod
mov word [bp+4], ax
mov word [bp+6], dx
mov ax, 10
xor dx, dx
push dx
push ax
lea ax, [bp-6]
push ax
call SR_asldiv
L_clib_41:
cmp word [bp-4], 0
jg L_clib_40
jne L_clib_43
cmp word [bp-6], 0
ja L_clib_40
L_clib_43:
L_clib_42:
push word [bp-2]
lea ax, [bp-17]
push ax
call print
add sp, 4
mov sp, bp
pop bp
ret
L_clib_31:
push bp
mov bp, sp
sub sp, 18
jmp L_clib_32
ALIGN 2
printUInt:
jmp L_clib_45
L_clib_46:
mov word [bp-2], 0
mov word [bp-4], 10000
mov ax, word [bp+4]
test ax, ax
jne L_clib_47
mov word [bp-4], 1
jmp L_clib_48
L_clib_47:
jmp L_clib_50
L_clib_49:
mov ax, word [bp-4]
xor dx, dx
mov cx, 10
div cx
mov word [bp-4], ax
L_clib_50:
mov ax, word [bp+4]
xor dx, dx
div word [bp-4]
test ax, ax
je L_clib_49
L_clib_51:
L_clib_48:
jmp L_clib_53
L_clib_52:
mov ax, word [bp+4]
xor dx, dx
div word [bp-4]
add al, 48
mov si, word [bp-2]
lea dx, [bp-10]
add si, dx
mov byte [si], al
inc word [bp-2]
mov ax, word [bp+4]
xor dx, dx
div word [bp-4]
mov word [bp+4], dx
mov ax, word [bp-4]
xor dx, dx
mov cx, 10
div cx
mov word [bp-4], ax
L_clib_53:
mov ax, word [bp-4]
test ax, ax
jne L_clib_52
L_clib_54:
push word [bp-2]
lea ax, [bp-10]
push ax
call print
add sp, 4
mov sp, bp
pop bp
ret
L_clib_45:
push bp
mov bp, sp
sub sp, 10
jmp L_clib_46
ALIGN 2
printULong:
jmp L_clib_56
L_clib_57:
mov word [bp-2], 0
mov word [bp-6], 51712
mov word [bp-4], 15258
mov ax, word [bp+4]
mov dx, word [bp+6]
or dx, ax
jne L_clib_58
mov word [bp-6], 1
mov word [bp-4], 0
jmp L_clib_59
L_clib_58:
jmp L_clib_61
L_clib_60:
mov ax, 10
xor dx, dx
push dx
push ax
lea ax, [bp-6]
push ax
call SR_asuldiv
L_clib_61:
push word [bp-4]
push word [bp-6]
push word [bp+6]
push word [bp+4]
call SR_uldiv
or dx, ax
je L_clib_60
L_clib_62:
L_clib_59:
jmp L_clib_64
L_clib_63:
push word [bp-4]
push word [bp-6]
push word [bp+6]
push word [bp+4]
call SR_uldiv
add al, 48
mov si, word [bp-2]
lea dx, [bp-17]
add si, dx
mov byte [si], al
inc word [bp-2]
push word [bp-4]
push word [bp-6]
lea ax, [bp+4]
push ax
call SR_asilmod
mov ax, 10
xor dx, dx
push dx
push ax
lea ax, [bp-6]
push ax
call SR_asuldiv
L_clib_64:
mov ax, word [bp-6]
mov dx, word [bp-4]
or dx, ax
jne L_clib_63
L_clib_65:
push word [bp-2]
lea ax, [bp-17]
push ax
call print
add sp, 4
mov sp, bp
pop bp
ret
L_clib_56:
push bp
mov bp, sp
sub sp, 18
jmp L_clib_57
ALIGN 2
printByte:
jmp L_clib_67
L_clib_68:
mov al, byte [bp+4]
cbw
mov cx, 4
sar ax, cl
and ax, 15
mov byte [bp-1], al
cmp byte [bp-1], 9
jle L_clib_69
mov al, byte [bp-1]
cbw
sub ax, 10
add ax, 65
jmp L_clib_70
L_clib_69:
mov al, byte [bp-1]
cbw
add ax, 48
L_clib_70:
mov byte [bp-3], al
mov al, byte [bp+4]
and al, 15
mov byte [bp-1], al
cmp byte [bp-1], 9
jle L_clib_71
mov al, byte [bp-1]
cbw
sub ax, 10
add ax, 65
jmp L_clib_72
L_clib_71:
mov al, byte [bp-1]
cbw
add ax, 48
L_clib_72:
mov byte [bp-2], al
mov ax, 2
push ax
lea ax, [bp-3]
push ax
call print
add sp, 4
mov sp, bp
pop bp
ret
L_clib_67:
push bp
mov bp, sp
sub sp, 4
jmp L_clib_68
ALIGN 2
printWord:
jmp L_clib_74
L_clib_75:
mov word [bp-2], 3
jmp L_clib_77
L_clib_76:
mov ax, word [bp+4]
and ax, 15
mov byte [bp-3], al
cmp byte [bp-3], 9
jle L_clib_80
mov al, byte [bp-3]
cbw
sub ax, 10
add ax, 65
jmp L_clib_81
L_clib_80:
mov al, byte [bp-3]
cbw
add ax, 48
L_clib_81:
mov si, word [bp-2]
lea dx, [bp-7]
add si, dx
mov byte [si], al
mov ax, word [bp+4]
mov cx, 4
sar ax, cl
mov word [bp+4], ax
L_clib_79:
dec word [bp-2]
L_clib_77:
cmp word [bp-2], 0
jge L_clib_76
L_clib_78:
mov ax, 4
push ax
lea ax, [bp-7]
push ax
call print
add sp, 4
mov sp, bp
pop bp
ret
L_clib_74:
push bp
mov bp, sp
sub sp, 8
jmp L_clib_75
ALIGN 2
printDWord:
jmp L_clib_83
L_clib_84:
lea ax, [bp+4]
mov si, ax
mov ax, word [si]
mov word [bp-6], ax
lea ax, [bp+4]
mov si, ax
add si, 2
mov ax, word [si]
mov word [bp-8], ax
mov word [bp-2], 3
jmp L_clib_86
L_clib_85:
mov ax, word [bp-6]
and ax, 15
mov byte [bp-3], al
cmp byte [bp-3], 9
jle L_clib_89
mov al, byte [bp-3]
cbw
sub ax, 10
add ax, 65
jmp L_clib_90
L_clib_89:
mov al, byte [bp-3]
cbw
add ax, 48
L_clib_90:
mov dx, word [bp-2]
add dx, 4
mov si, dx
lea dx, [bp-16]
add si, dx
mov byte [si], al
mov ax, word [bp-6]
mov cx, 4
sar ax, cl
mov word [bp-6], ax
mov ax, word [bp-8]
and ax, 15
mov byte [bp-3], al
cmp byte [bp-3], 9
jle L_clib_91
mov al, byte [bp-3]
cbw
sub ax, 10
add ax, 65
jmp L_clib_92
L_clib_91:
mov al, byte [bp-3]
cbw
add ax, 48
L_clib_92:
mov si, word [bp-2]
lea dx, [bp-16]
add si, dx
mov byte [si], al
mov ax, word [bp-8]
mov cx, 4
sar ax, cl
mov word [bp-8], ax
L_clib_88:
dec word [bp-2]
L_clib_86:
cmp word [bp-2], 0
jge L_clib_85
L_clib_87:
mov ax, 8
push ax
lea ax, [bp-16]
push ax
call print
add sp, 4
mov sp, bp
pop bp
ret
L_clib_83:
push bp
mov bp, sp
sub sp, 16
jmp L_clib_84