83 lines
2.0 KiB
VHDL
83 lines
2.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vga_timing is
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port(
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clk: in std_logic;
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rst: in std_logic;
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HS: out std_logic;
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VS: out std_logic;
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pixel_x: out std_logic_vector(9 downto 0);
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pixel_y: out std_logic_vector(9 downto 0);
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last_column: out std_logic;
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last_row: out std_logic;
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blank: out std_logic
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);
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end vga_timing;
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architecture behavior of vga_timing is
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signal pixel_en: std_logic := '0';
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signal column: unsigned(9 downto 0);
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signal column_next: unsigned(9 downto 0);
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signal row: unsigned(9 downto 0);
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signal row_next: unsigned(9 downto 0);
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begin
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-- pixel clock
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process(clk, rst)
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begin
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if(rst = '1') then
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pixel_en <= '0';
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elsif(clk'event and clk='1') then
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pixel_en <= not pixel_en;
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end if;
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end process;
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-- register for HS counter
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process(rst,clk)
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begin
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if(rst = '1') then
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column <= (others=>'0');
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elsif(clk'event and clk = '1') then
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if(pixel_en = '1') then
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column <= column_next;
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end if;
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end if;
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end process;
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-- next state HS counter
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column_next <= (others=>'0') when column = 799 else
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column + 1;
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-- output logic for HS counter
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last_column <= '1' when column = 639 else
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'0';
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HS <= '0' when ((column > 655) and (column < 752)) else
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'1';
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pixel_x <= std_logic_vector(column);
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-- register for VS counter
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process(rst,clk, pixel_en, column)
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begin
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if(rst = '1') then
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row <= (others=>'0');
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elsif(clk'event and clk = '1') then
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if(pixel_en = '1' and column = 799) then -- only increment if HS is 799 and the pixel enable is high
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row <= row_next;
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end if;
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end if;
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end process;
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-- next state VS counter
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row_next <= (others=>'0') when row = 520 else
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row + 1;
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-- output logic for VS counter
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last_row <= '1' when row = 479 else
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'0';
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VS <= '0' when ((row > 489) and (row < 492)) else
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'1';
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pixel_y <= std_logic_vector(row);
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-- blank signal
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blank <= '1' when (row > 479) or (column > 639) else
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'0';
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end behavior; |